1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <mach/clock.h> 28 #include <mach/clockdomain.h> 29 #include <mach/sram.h> 30 #include <mach/cpu.h> 31 #include <asm/div64.h> 32 33 #include "memory.h" 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 #define MAX_CLOCK_ENABLE_WAIT 100000 43 44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 45 #define DPLL_MIN_MULTIPLIER 1 46 #define DPLL_MIN_DIVIDER 1 47 48 /* Possible error results from _dpll_test_mult */ 49 #define DPLL_MULT_UNDERFLOW (1 << 0) 50 51 /* 52 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 53 * The higher the scale factor, the greater the risk of arithmetic overflow, 54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 55 * must be a power of DPLL_SCALE_BASE. 56 */ 57 #define DPLL_SCALE_FACTOR 64 58 #define DPLL_SCALE_BASE 2 59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 61 62 u8 cpu_mask; 63 64 /*------------------------------------------------------------------------- 65 * OMAP2/3 specific clock functions 66 *-------------------------------------------------------------------------*/ 67 68 /** 69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 70 * @clk: OMAP clock struct ptr to use 71 * 72 * Convert a clockdomain name stored in a struct clk 'clk' into a 73 * clockdomain pointer, and save it into the struct clk. Intended to be 74 * called during clk_register(). No return value. 75 */ 76 void omap2_init_clk_clkdm(struct clk *clk) 77 { 78 struct clockdomain *clkdm; 79 80 if (!clk->clkdm_name) 81 return; 82 83 clkdm = clkdm_lookup(clk->clkdm_name); 84 if (clkdm) { 85 pr_debug("clock: associated clk %s to clkdm %s\n", 86 clk->name, clk->clkdm_name); 87 clk->clkdm = clkdm; 88 } else { 89 pr_debug("clock: could not associate clk %s to " 90 "clkdm %s\n", clk->name, clk->clkdm_name); 91 } 92 } 93 94 /** 95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 96 * @clk: OMAP clock struct ptr to use 97 * 98 * Given a pointer to a source-selectable struct clk, read the hardware 99 * register and determine what its parent is currently set to. Update the 100 * clk->parent field with the appropriate clk ptr. 101 */ 102 void omap2_init_clksel_parent(struct clk *clk) 103 { 104 const struct clksel *clks; 105 const struct clksel_rate *clkr; 106 u32 r, found = 0; 107 108 if (!clk->clksel) 109 return; 110 111 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 112 r >>= __ffs(clk->clksel_mask); 113 114 for (clks = clk->clksel; clks->parent && !found; clks++) { 115 for (clkr = clks->rates; clkr->div && !found; clkr++) { 116 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 117 if (clk->parent != clks->parent) { 118 pr_debug("clock: inited %s parent " 119 "to %s (was %s)\n", 120 clk->name, clks->parent->name, 121 ((clk->parent) ? 122 clk->parent->name : "NULL")); 123 clk->parent = clks->parent; 124 }; 125 found = 1; 126 } 127 } 128 } 129 130 if (!found) 131 printk(KERN_ERR "clock: init parent: could not find " 132 "regval %0x for clock %s\n", r, clk->name); 133 134 return; 135 } 136 137 /* Returns the DPLL rate */ 138 u32 omap2_get_dpll_rate(struct clk *clk) 139 { 140 long long dpll_clk; 141 u32 dpll_mult, dpll_div, dpll; 142 struct dpll_data *dd; 143 144 dd = clk->dpll_data; 145 /* REVISIT: What do we return on error? */ 146 if (!dd) 147 return 0; 148 149 dpll = __raw_readl(dd->mult_div1_reg); 150 dpll_mult = dpll & dd->mult_mask; 151 dpll_mult >>= __ffs(dd->mult_mask); 152 dpll_div = dpll & dd->div1_mask; 153 dpll_div >>= __ffs(dd->div1_mask); 154 155 dpll_clk = (long long)clk->parent->rate * dpll_mult; 156 do_div(dpll_clk, dpll_div + 1); 157 158 return dpll_clk; 159 } 160 161 /* 162 * Used for clocks that have the same value as the parent clock, 163 * divided by some factor 164 */ 165 void omap2_fixed_divisor_recalc(struct clk *clk) 166 { 167 WARN_ON(!clk->fixed_div); 168 169 clk->rate = clk->parent->rate / clk->fixed_div; 170 171 if (clk->flags & RATE_PROPAGATES) 172 propagate_rate(clk); 173 } 174 175 /** 176 * omap2_wait_clock_ready - wait for clock to enable 177 * @reg: physical address of clock IDLEST register 178 * @mask: value to mask against to determine if the clock is active 179 * @name: name of the clock (for printk) 180 * 181 * Returns 1 if the clock enabled in time, or 0 if it failed to enable 182 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. 183 */ 184 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) 185 { 186 int i = 0; 187 int ena = 0; 188 189 /* 190 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 191 * 34xx reverses this, just to keep us on our toes 192 */ 193 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { 194 ena = mask; 195 } else if (cpu_mask & RATE_IN_343X) { 196 ena = 0; 197 } 198 199 /* Wait for lock */ 200 while (((__raw_readl(reg) & mask) != ena) && 201 (i++ < MAX_CLOCK_ENABLE_WAIT)) { 202 udelay(1); 203 } 204 205 if (i < MAX_CLOCK_ENABLE_WAIT) 206 pr_debug("Clock %s stable after %d loops\n", name, i); 207 else 208 printk(KERN_ERR "Clock %s didn't enable in %d tries\n", 209 name, MAX_CLOCK_ENABLE_WAIT); 210 211 212 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; 213 }; 214 215 216 /* 217 * Note: We don't need special code here for INVERT_ENABLE 218 * for the time being since INVERT_ENABLE only applies to clocks enabled by 219 * CM_CLKEN_PLL 220 */ 221 static void omap2_clk_wait_ready(struct clk *clk) 222 { 223 void __iomem *reg, *other_reg, *st_reg; 224 u32 bit; 225 226 /* 227 * REVISIT: This code is pretty ugly. It would be nice to generalize 228 * it and pull it into struct clk itself somehow. 229 */ 230 reg = clk->enable_reg; 231 if ((((u32)reg & 0xff) >= CM_FCLKEN1) && 232 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) 233 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ 234 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && 235 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) 236 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ 237 else 238 return; 239 240 /* REVISIT: What are the appropriate exclusions for 34XX? */ 241 /* No check for DSS or cam clocks */ 242 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ 243 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || 244 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || 245 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) 246 return; 247 } 248 249 /* REVISIT: What are the appropriate exclusions for 34XX? */ 250 /* OMAP3: ignore DSS-mod clocks */ 251 if (cpu_is_omap34xx() && 252 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || 253 ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && 254 clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) 255 return; 256 257 /* Check if both functional and interface clocks 258 * are running. */ 259 bit = 1 << clk->enable_bit; 260 if (!(__raw_readl(other_reg) & bit)) 261 return; 262 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ 263 264 omap2_wait_clock_ready(st_reg, bit, clk->name); 265 } 266 267 /* Enables clock without considering parent dependencies or use count 268 * REVISIT: Maybe change this to use clk->enable like on omap1? 269 */ 270 int _omap2_clk_enable(struct clk *clk) 271 { 272 u32 regval32; 273 274 if (clk->ops && clk->ops->enable) 275 return clk->ops->enable(clk); 276 277 if (unlikely(clk->enable_reg == NULL)) { 278 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 279 clk->name); 280 return 0; /* REVISIT: -EINVAL */ 281 } 282 283 regval32 = __raw_readl(clk->enable_reg); 284 if (clk->flags & INVERT_ENABLE) 285 regval32 &= ~(1 << clk->enable_bit); 286 else 287 regval32 |= (1 << clk->enable_bit); 288 __raw_writel(regval32, clk->enable_reg); 289 wmb(); 290 291 omap2_clk_wait_ready(clk); 292 293 return 0; 294 } 295 296 /* Disables clock without considering parent dependencies or use count */ 297 void _omap2_clk_disable(struct clk *clk) 298 { 299 u32 regval32; 300 301 if (clk->ops && clk->ops->disable) { 302 clk->ops->disable(clk); 303 return; 304 } 305 306 if (clk->enable_reg == NULL) { 307 /* 308 * 'Independent' here refers to a clock which is not 309 * controlled by its parent. 310 */ 311 printk(KERN_ERR "clock: clk_disable called on independent " 312 "clock %s which has no enable_reg\n", clk->name); 313 return; 314 } 315 316 regval32 = __raw_readl(clk->enable_reg); 317 if (clk->flags & INVERT_ENABLE) 318 regval32 |= (1 << clk->enable_bit); 319 else 320 regval32 &= ~(1 << clk->enable_bit); 321 __raw_writel(regval32, clk->enable_reg); 322 wmb(); 323 } 324 325 void omap2_clk_disable(struct clk *clk) 326 { 327 if (clk->usecount > 0 && !(--clk->usecount)) { 328 _omap2_clk_disable(clk); 329 if (likely((u32)clk->parent)) 330 omap2_clk_disable(clk->parent); 331 if (clk->clkdm) 332 omap2_clkdm_clk_disable(clk->clkdm, clk); 333 334 } 335 } 336 337 int omap2_clk_enable(struct clk *clk) 338 { 339 int ret = 0; 340 341 if (clk->usecount++ == 0) { 342 if (likely((u32)clk->parent)) 343 ret = omap2_clk_enable(clk->parent); 344 345 if (unlikely(ret != 0)) { 346 clk->usecount--; 347 return ret; 348 } 349 350 if (clk->clkdm) 351 omap2_clkdm_clk_enable(clk->clkdm, clk); 352 353 ret = _omap2_clk_enable(clk); 354 355 if (unlikely(ret != 0)) { 356 if (clk->clkdm) 357 omap2_clkdm_clk_disable(clk->clkdm, clk); 358 359 if (clk->parent) { 360 omap2_clk_disable(clk->parent); 361 clk->usecount--; 362 } 363 } 364 } 365 366 return ret; 367 } 368 369 /* 370 * Used for clocks that are part of CLKSEL_xyz governed clocks. 371 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 372 */ 373 void omap2_clksel_recalc(struct clk *clk) 374 { 375 u32 div = 0; 376 377 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 378 379 div = omap2_clksel_get_divisor(clk); 380 if (div == 0) 381 return; 382 383 if (unlikely(clk->rate == clk->parent->rate / div)) 384 return; 385 clk->rate = clk->parent->rate / div; 386 387 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); 388 389 if (unlikely(clk->flags & RATE_PROPAGATES)) 390 propagate_rate(clk); 391 } 392 393 /** 394 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 395 * @clk: OMAP struct clk ptr to inspect 396 * @src_clk: OMAP struct clk ptr of the parent clk to search for 397 * 398 * Scan the struct clksel array associated with the clock to find 399 * the element associated with the supplied parent clock address. 400 * Returns a pointer to the struct clksel on success or NULL on error. 401 */ 402 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 403 struct clk *src_clk) 404 { 405 const struct clksel *clks; 406 407 if (!clk->clksel) 408 return NULL; 409 410 for (clks = clk->clksel; clks->parent; clks++) { 411 if (clks->parent == src_clk) 412 break; /* Found the requested parent */ 413 } 414 415 if (!clks->parent) { 416 printk(KERN_ERR "clock: Could not find parent clock %s in " 417 "clksel array of clock %s\n", src_clk->name, 418 clk->name); 419 return NULL; 420 } 421 422 return clks; 423 } 424 425 /** 426 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 427 * @clk: OMAP struct clk to use 428 * @target_rate: desired clock rate 429 * @new_div: ptr to where we should store the divisor 430 * 431 * Finds 'best' divider value in an array based on the source and target 432 * rates. The divider array must be sorted with smallest divider first. 433 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 434 * they are only settable as part of virtual_prcm set. 435 * 436 * Returns the rounded clock rate or returns 0xffffffff on error. 437 */ 438 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 439 u32 *new_div) 440 { 441 unsigned long test_rate; 442 const struct clksel *clks; 443 const struct clksel_rate *clkr; 444 u32 last_div = 0; 445 446 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", 447 clk->name, target_rate); 448 449 *new_div = 1; 450 451 clks = omap2_get_clksel_by_parent(clk, clk->parent); 452 if (clks == NULL) 453 return ~0; 454 455 for (clkr = clks->rates; clkr->div; clkr++) { 456 if (!(clkr->flags & cpu_mask)) 457 continue; 458 459 /* Sanity check */ 460 if (clkr->div <= last_div) 461 printk(KERN_ERR "clock: clksel_rate table not sorted " 462 "for clock %s", clk->name); 463 464 last_div = clkr->div; 465 466 test_rate = clk->parent->rate / clkr->div; 467 468 if (test_rate <= target_rate) 469 break; /* found it */ 470 } 471 472 if (!clkr->div) { 473 printk(KERN_ERR "clock: Could not find divisor for target " 474 "rate %ld for clock %s parent %s\n", target_rate, 475 clk->name, clk->parent->name); 476 return ~0; 477 } 478 479 *new_div = clkr->div; 480 481 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, 482 (clk->parent->rate / clkr->div)); 483 484 return (clk->parent->rate / clkr->div); 485 } 486 487 /** 488 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 489 * @clk: OMAP struct clk to use 490 * @target_rate: desired clock rate 491 * 492 * Compatibility wrapper for OMAP clock framework 493 * Finds best target rate based on the source clock and possible dividers. 494 * rates. The divider array must be sorted with smallest divider first. 495 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 496 * they are only settable as part of virtual_prcm set. 497 * 498 * Returns the rounded clock rate or returns 0xffffffff on error. 499 */ 500 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 501 { 502 u32 new_div; 503 504 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 505 } 506 507 508 /* Given a clock and a rate apply a clock specific rounding function */ 509 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 510 { 511 if (clk->round_rate != NULL) 512 return clk->round_rate(clk, rate); 513 514 if (clk->flags & RATE_FIXED) 515 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 516 "on fixed-rate clock %s\n", clk->name); 517 518 return clk->rate; 519 } 520 521 /** 522 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 523 * @clk: OMAP struct clk to use 524 * @field_val: register field value to find 525 * 526 * Given a struct clk of a rate-selectable clksel clock, and a register field 527 * value to search for, find the corresponding clock divisor. The register 528 * field value should be pre-masked and shifted down so the LSB is at bit 0 529 * before calling. Returns 0 on error 530 */ 531 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 532 { 533 const struct clksel *clks; 534 const struct clksel_rate *clkr; 535 536 clks = omap2_get_clksel_by_parent(clk, clk->parent); 537 if (clks == NULL) 538 return 0; 539 540 for (clkr = clks->rates; clkr->div; clkr++) { 541 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 542 break; 543 } 544 545 if (!clkr->div) { 546 printk(KERN_ERR "clock: Could not find fieldval %d for " 547 "clock %s parent %s\n", field_val, clk->name, 548 clk->parent->name); 549 return 0; 550 } 551 552 return clkr->div; 553 } 554 555 /** 556 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 557 * @clk: OMAP struct clk to use 558 * @div: integer divisor to search for 559 * 560 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 561 * find the corresponding register field value. The return register value is 562 * the value before left-shifting. Returns 0xffffffff on error 563 */ 564 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 565 { 566 const struct clksel *clks; 567 const struct clksel_rate *clkr; 568 569 /* should never happen */ 570 WARN_ON(div == 0); 571 572 clks = omap2_get_clksel_by_parent(clk, clk->parent); 573 if (clks == NULL) 574 return 0; 575 576 for (clkr = clks->rates; clkr->div; clkr++) { 577 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 578 break; 579 } 580 581 if (!clkr->div) { 582 printk(KERN_ERR "clock: Could not find divisor %d for " 583 "clock %s parent %s\n", div, clk->name, 584 clk->parent->name); 585 return 0; 586 } 587 588 return clkr->val; 589 } 590 591 /** 592 * omap2_get_clksel - find clksel register addr & field mask for a clk 593 * @clk: struct clk to use 594 * @field_mask: ptr to u32 to store the register field mask 595 * 596 * Returns the address of the clksel register upon success or NULL on error. 597 */ 598 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 599 { 600 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) 601 return NULL; 602 603 *field_mask = clk->clksel_mask; 604 605 return clk->clksel_reg; 606 } 607 608 /** 609 * omap2_clksel_get_divisor - get current divider applied to parent clock. 610 * @clk: OMAP struct clk to use. 611 * 612 * Returns the integer divisor upon success or 0 on error. 613 */ 614 u32 omap2_clksel_get_divisor(struct clk *clk) 615 { 616 u32 field_mask, field_val; 617 void __iomem *div_addr; 618 619 div_addr = omap2_get_clksel(clk, &field_mask); 620 if (div_addr == NULL) 621 return 0; 622 623 field_val = __raw_readl(div_addr) & field_mask; 624 field_val >>= __ffs(field_mask); 625 626 return omap2_clksel_to_divisor(clk, field_val); 627 } 628 629 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 630 { 631 u32 field_mask, field_val, reg_val, validrate, new_div = 0; 632 void __iomem *div_addr; 633 634 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 635 if (validrate != rate) 636 return -EINVAL; 637 638 div_addr = omap2_get_clksel(clk, &field_mask); 639 if (div_addr == NULL) 640 return -EINVAL; 641 642 field_val = omap2_divisor_to_clksel(clk, new_div); 643 if (field_val == ~0) 644 return -EINVAL; 645 646 reg_val = __raw_readl(div_addr); 647 reg_val &= ~field_mask; 648 reg_val |= (field_val << __ffs(field_mask)); 649 __raw_writel(reg_val, div_addr); 650 wmb(); 651 652 clk->rate = clk->parent->rate / new_div; 653 654 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 655 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, 656 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); 657 wmb(); 658 } 659 660 return 0; 661 } 662 663 664 /* Set the clock rate for a clock source */ 665 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 666 { 667 int ret = -EINVAL; 668 669 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 670 671 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 672 rate table mechanism, driven by mpu_speed */ 673 if (clk->flags & CONFIG_PARTICIPANT) 674 return -EINVAL; 675 676 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 677 if (clk->set_rate != NULL) 678 ret = clk->set_rate(clk, rate); 679 680 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 681 propagate_rate(clk); 682 683 return ret; 684 } 685 686 /* 687 * Converts encoded control register address into a full address 688 * On error, *src_addr will be returned as 0. 689 */ 690 static u32 omap2_clksel_get_src_field(void __iomem **src_addr, 691 struct clk *src_clk, u32 *field_mask, 692 struct clk *clk, u32 *parent_div) 693 { 694 const struct clksel *clks; 695 const struct clksel_rate *clkr; 696 697 *parent_div = 0; 698 *src_addr = NULL; 699 700 clks = omap2_get_clksel_by_parent(clk, src_clk); 701 if (clks == NULL) 702 return 0; 703 704 for (clkr = clks->rates; clkr->div; clkr++) { 705 if (clkr->flags & (cpu_mask | DEFAULT_RATE)) 706 break; /* Found the default rate for this platform */ 707 } 708 709 if (!clkr->div) { 710 printk(KERN_ERR "clock: Could not find default rate for " 711 "clock %s parent %s\n", clk->name, 712 src_clk->parent->name); 713 return 0; 714 } 715 716 /* Should never happen. Add a clksel mask to the struct clk. */ 717 WARN_ON(clk->clksel_mask == 0); 718 719 *field_mask = clk->clksel_mask; 720 *src_addr = clk->clksel_reg; 721 *parent_div = clkr->div; 722 723 return clkr->val; 724 } 725 726 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 727 { 728 void __iomem *src_addr; 729 u32 field_val, field_mask, reg_val, parent_div; 730 731 if (unlikely(clk->flags & CONFIG_PARTICIPANT)) 732 return -EINVAL; 733 734 if (!clk->clksel) 735 return -EINVAL; 736 737 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 738 &field_mask, clk, &parent_div); 739 if (src_addr == NULL) 740 return -EINVAL; 741 742 if (clk->usecount > 0) 743 _omap2_clk_disable(clk); 744 745 /* Set new source value (previous dividers if any in effect) */ 746 reg_val = __raw_readl(src_addr) & ~field_mask; 747 reg_val |= (field_val << __ffs(field_mask)); 748 __raw_writel(reg_val, src_addr); 749 wmb(); 750 751 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 752 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 753 wmb(); 754 } 755 756 if (clk->usecount > 0) 757 _omap2_clk_enable(clk); 758 759 clk->parent = new_parent; 760 761 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 762 clk->rate = new_parent->rate; 763 764 if (parent_div > 0) 765 clk->rate /= parent_div; 766 767 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 768 clk->name, clk->parent->name, clk->rate); 769 770 if (unlikely(clk->flags & RATE_PROPAGATES)) 771 propagate_rate(clk); 772 773 return 0; 774 } 775 776 /* DPLL rate rounding code */ 777 778 /** 779 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 780 * @clk: struct clk * of the DPLL 781 * @tolerance: maximum rate error tolerance 782 * 783 * Set the maximum DPLL rate error tolerance for the rate rounding 784 * algorithm. The rate tolerance is an attempt to balance DPLL power 785 * saving (the least divider value "n") vs. rate fidelity (the least 786 * difference between the desired DPLL target rate and the rounded 787 * rate out of the algorithm). So, increasing the tolerance is likely 788 * to decrease DPLL power consumption and increase DPLL rate error. 789 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 790 * DPLL; or 0 upon success. 791 */ 792 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 793 { 794 if (!clk || !clk->dpll_data) 795 return -EINVAL; 796 797 clk->dpll_data->rate_tolerance = tolerance; 798 799 return 0; 800 } 801 802 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) 803 { 804 unsigned long long num; 805 806 num = (unsigned long long)parent_rate * m; 807 do_div(num, n); 808 return num; 809 } 810 811 /* 812 * _dpll_test_mult - test a DPLL multiplier value 813 * @m: pointer to the DPLL m (multiplier) value under test 814 * @n: current DPLL n (divider) value under test 815 * @new_rate: pointer to storage for the resulting rounded rate 816 * @target_rate: the desired DPLL rate 817 * @parent_rate: the DPLL's parent clock rate 818 * 819 * This code tests a DPLL multiplier value, ensuring that the 820 * resulting rate will not be higher than the target_rate, and that 821 * the multiplier value itself is valid for the DPLL. Initially, the 822 * integer pointed to by the m argument should be prescaled by 823 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 824 * a non-scaled m upon return. This non-scaled m will result in a 825 * new_rate as close as possible to target_rate (but not greater than 826 * target_rate) given the current (parent_rate, n, prescaled m) 827 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 828 * non-scaled m attempted to underflow, which can allow the calling 829 * function to bail out early; or 0 upon success. 830 */ 831 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 832 unsigned long target_rate, 833 unsigned long parent_rate) 834 { 835 int flags = 0, carry = 0; 836 837 /* Unscale m and round if necessary */ 838 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 839 carry = 1; 840 *m = (*m / DPLL_SCALE_FACTOR) + carry; 841 842 /* 843 * The new rate must be <= the target rate to avoid programming 844 * a rate that is impossible for the hardware to handle 845 */ 846 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 847 if (*new_rate > target_rate) { 848 (*m)--; 849 *new_rate = 0; 850 } 851 852 /* Guard against m underflow */ 853 if (*m < DPLL_MIN_MULTIPLIER) { 854 *m = DPLL_MIN_MULTIPLIER; 855 *new_rate = 0; 856 flags = DPLL_MULT_UNDERFLOW; 857 } 858 859 if (*new_rate == 0) 860 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 861 862 return flags; 863 } 864 865 /** 866 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 867 * @clk: struct clk * for a DPLL 868 * @target_rate: desired DPLL clock rate 869 * 870 * Given a DPLL, a desired target rate, and a rate tolerance, round 871 * the target rate to a possible, programmable rate for this DPLL. 872 * Rate tolerance is assumed to be set by the caller before this 873 * function is called. Attempts to select the minimum possible n 874 * within the tolerance to reduce power consumption. Stores the 875 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 876 * will not need to call this (expensive) function again. Returns ~0 877 * if the target rate cannot be rounded, either because the rate is 878 * too low or because the rate tolerance is set too tightly; or the 879 * rounded rate upon success. 880 */ 881 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 882 { 883 int m, n, r, e, scaled_max_m; 884 unsigned long scaled_rt_rp, new_rate; 885 int min_e = -1, min_e_m = -1, min_e_n = -1; 886 887 if (!clk || !clk->dpll_data) 888 return ~0; 889 890 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 891 "%ld\n", clk->name, target_rate); 892 893 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); 894 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; 895 896 clk->dpll_data->last_rounded_rate = 0; 897 898 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { 899 900 /* Compute the scaled DPLL multiplier, based on the divider */ 901 m = scaled_rt_rp * n; 902 903 /* 904 * Since we're counting n down, a m overflow means we can 905 * can immediately skip to the next n 906 */ 907 if (m > scaled_max_m) 908 continue; 909 910 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 911 clk->parent->rate); 912 913 e = target_rate - new_rate; 914 pr_debug("clock: n = %d: m = %d: rate error is %d " 915 "(new_rate = %ld)\n", n, m, e, new_rate); 916 917 if (min_e == -1 || 918 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { 919 min_e = e; 920 min_e_m = m; 921 min_e_n = n; 922 923 pr_debug("clock: found new least error %d\n", min_e); 924 } 925 926 /* 927 * Since we're counting n down, a m underflow means we 928 * can bail out completely (since as n decreases in 929 * the next iteration, there's no way that m can 930 * increase beyond the current m) 931 */ 932 if (r & DPLL_MULT_UNDERFLOW) 933 break; 934 } 935 936 if (min_e < 0) { 937 pr_debug("clock: error: target rate or tolerance too low\n"); 938 return ~0; 939 } 940 941 clk->dpll_data->last_rounded_m = min_e_m; 942 clk->dpll_data->last_rounded_n = min_e_n; 943 clk->dpll_data->last_rounded_rate = 944 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); 945 946 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 947 min_e, min_e_m, min_e_n); 948 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 949 clk->dpll_data->last_rounded_rate, target_rate); 950 951 return clk->dpll_data->last_rounded_rate; 952 } 953 954 /*------------------------------------------------------------------------- 955 * Omap2 clock reset and init functions 956 *-------------------------------------------------------------------------*/ 957 958 #ifdef CONFIG_OMAP_RESET_CLOCKS 959 void omap2_clk_disable_unused(struct clk *clk) 960 { 961 u32 regval32, v; 962 963 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 964 965 regval32 = __raw_readl(clk->enable_reg); 966 if ((regval32 & (1 << clk->enable_bit)) == v) 967 return; 968 969 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 970 _omap2_clk_disable(clk); 971 } 972 #endif 973