1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/delay.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 #include <linux/bitops.h> 25 26 #include <plat/clock.h> 27 #include <plat/clockdomain.h> 28 #include <plat/cpu.h> 29 #include <plat/prcm.h> 30 31 #include "clock.h" 32 #include "prm.h" 33 #include "prm-regbits-24xx.h" 34 #include "cm.h" 35 #include "cm-regbits-24xx.h" 36 #include "cm-regbits-34xx.h" 37 38 u8 cpu_mask; 39 40 /*------------------------------------------------------------------------- 41 * OMAP2/3/4 specific clock functions 42 *-------------------------------------------------------------------------*/ 43 44 /* Private functions */ 45 46 /** 47 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 48 * @clk: struct clk * belonging to the module 49 * 50 * If the necessary clocks for the OMAP hardware IP block that 51 * corresponds to clock @clk are enabled, then wait for the module to 52 * indicate readiness (i.e., to leave IDLE). This code does not 53 * belong in the clock code and will be moved in the medium term to 54 * module-dependent code. No return value. 55 */ 56 static void _omap2_module_wait_ready(struct clk *clk) 57 { 58 void __iomem *companion_reg, *idlest_reg; 59 u8 other_bit, idlest_bit, idlest_val; 60 61 /* Not all modules have multiple clocks that their IDLEST depends on */ 62 if (clk->ops->find_companion) { 63 clk->ops->find_companion(clk, &companion_reg, &other_bit); 64 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 65 return; 66 } 67 68 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 69 70 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, 71 clk->name); 72 } 73 74 /* Enables clock without considering parent dependencies or use count 75 * REVISIT: Maybe change this to use clk->enable like on omap1? 76 */ 77 static int _omap2_clk_enable(struct clk *clk) 78 { 79 return clk->ops->enable(clk); 80 } 81 82 /* Disables clock without considering parent dependencies or use count */ 83 static void _omap2_clk_disable(struct clk *clk) 84 { 85 clk->ops->disable(clk); 86 } 87 88 /* Public functions */ 89 90 /** 91 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 92 * @clk: OMAP clock struct ptr to use 93 * 94 * Convert a clockdomain name stored in a struct clk 'clk' into a 95 * clockdomain pointer, and save it into the struct clk. Intended to be 96 * called during clk_register(). No return value. 97 */ 98 void omap2_init_clk_clkdm(struct clk *clk) 99 { 100 struct clockdomain *clkdm; 101 102 if (!clk->clkdm_name) 103 return; 104 105 clkdm = clkdm_lookup(clk->clkdm_name); 106 if (clkdm) { 107 pr_debug("clock: associated clk %s to clkdm %s\n", 108 clk->name, clk->clkdm_name); 109 clk->clkdm = clkdm; 110 } else { 111 pr_debug("clock: could not associate clk %s to " 112 "clkdm %s\n", clk->name, clk->clkdm_name); 113 } 114 } 115 116 /** 117 * omap2_clk_dflt_find_companion - find companion clock to @clk 118 * @clk: struct clk * to find the companion clock of 119 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 120 * @other_bit: u8 ** to return the companion clock bit shift in 121 * 122 * Note: We don't need special code here for INVERT_ENABLE for the 123 * time being since INVERT_ENABLE only applies to clocks enabled by 124 * CM_CLKEN_PLL 125 * 126 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 127 * just a matter of XORing the bits. 128 * 129 * Some clocks don't have companion clocks. For example, modules with 130 * only an interface clock (such as MAILBOXES) don't have a companion 131 * clock. Right now, this code relies on the hardware exporting a bit 132 * in the correct companion register that indicates that the 133 * nonexistent 'companion clock' is active. Future patches will 134 * associate this type of code with per-module data structures to 135 * avoid this issue, and remove the casts. No return value. 136 */ 137 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 138 u8 *other_bit) 139 { 140 u32 r; 141 142 /* 143 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 144 * it's just a matter of XORing the bits. 145 */ 146 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 147 148 *other_reg = (__force void __iomem *)r; 149 *other_bit = clk->enable_bit; 150 } 151 152 /** 153 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 154 * @clk: struct clk * to find IDLEST info for 155 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 156 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 157 * @idlest_val: u8 * to return the idle status indicator 158 * 159 * Return the CM_IDLEST register address and bit shift corresponding 160 * to the module that "owns" this clock. This default code assumes 161 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 162 * the IDLEST register address ID corresponds to the CM_*CLKEN 163 * register address ID (e.g., that CM_FCLKEN2 corresponds to 164 * CM_IDLEST2). This is not true for all modules. No return value. 165 */ 166 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 167 u8 *idlest_bit, u8 *idlest_val) 168 { 169 u32 r; 170 171 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 172 *idlest_reg = (__force void __iomem *)r; 173 *idlest_bit = clk->enable_bit; 174 175 /* 176 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 177 * 34xx reverses this, just to keep us on our toes 178 * AM35xx uses both, depending on the module. 179 */ 180 if (cpu_is_omap24xx()) 181 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 182 else if (cpu_is_omap34xx()) 183 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 184 else 185 BUG(); 186 187 } 188 189 int omap2_dflt_clk_enable(struct clk *clk) 190 { 191 u32 v; 192 193 if (unlikely(clk->enable_reg == NULL)) { 194 pr_err("clock.c: Enable for %s without enable code\n", 195 clk->name); 196 return 0; /* REVISIT: -EINVAL */ 197 } 198 199 v = __raw_readl(clk->enable_reg); 200 if (clk->flags & INVERT_ENABLE) 201 v &= ~(1 << clk->enable_bit); 202 else 203 v |= (1 << clk->enable_bit); 204 __raw_writel(v, clk->enable_reg); 205 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 206 207 if (clk->ops->find_idlest) 208 _omap2_module_wait_ready(clk); 209 210 return 0; 211 } 212 213 void omap2_dflt_clk_disable(struct clk *clk) 214 { 215 u32 v; 216 217 if (!clk->enable_reg) { 218 /* 219 * 'Independent' here refers to a clock which is not 220 * controlled by its parent. 221 */ 222 printk(KERN_ERR "clock: clk_disable called on independent " 223 "clock %s which has no enable_reg\n", clk->name); 224 return; 225 } 226 227 v = __raw_readl(clk->enable_reg); 228 if (clk->flags & INVERT_ENABLE) 229 v |= (1 << clk->enable_bit); 230 else 231 v &= ~(1 << clk->enable_bit); 232 __raw_writel(v, clk->enable_reg); 233 /* No OCP barrier needed here since it is a disable operation */ 234 } 235 236 const struct clkops clkops_omap2_dflt_wait = { 237 .enable = omap2_dflt_clk_enable, 238 .disable = omap2_dflt_clk_disable, 239 .find_companion = omap2_clk_dflt_find_companion, 240 .find_idlest = omap2_clk_dflt_find_idlest, 241 }; 242 243 const struct clkops clkops_omap2_dflt = { 244 .enable = omap2_dflt_clk_enable, 245 .disable = omap2_dflt_clk_disable, 246 }; 247 248 void omap2_clk_disable(struct clk *clk) 249 { 250 if (clk->usecount > 0 && !(--clk->usecount)) { 251 _omap2_clk_disable(clk); 252 if (clk->parent) 253 omap2_clk_disable(clk->parent); 254 if (clk->clkdm) 255 omap2_clkdm_clk_disable(clk->clkdm, clk); 256 257 } 258 } 259 260 int omap2_clk_enable(struct clk *clk) 261 { 262 int ret = 0; 263 264 if (clk->usecount++ == 0) { 265 if (clk->clkdm) 266 omap2_clkdm_clk_enable(clk->clkdm, clk); 267 268 if (clk->parent) { 269 ret = omap2_clk_enable(clk->parent); 270 if (ret) 271 goto err; 272 } 273 274 ret = _omap2_clk_enable(clk); 275 if (ret) { 276 if (clk->parent) 277 omap2_clk_disable(clk->parent); 278 279 goto err; 280 } 281 } 282 return ret; 283 284 err: 285 if (clk->clkdm) 286 omap2_clkdm_clk_disable(clk->clkdm, clk); 287 clk->usecount--; 288 return ret; 289 } 290 291 /* Set the clock rate for a clock source */ 292 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 293 { 294 int ret = -EINVAL; 295 296 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 297 298 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 299 if (clk->set_rate) 300 ret = clk->set_rate(clk, rate); 301 302 return ret; 303 } 304 305 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 306 { 307 if (!clk->clksel) 308 return -EINVAL; 309 310 if (clk->parent == new_parent) 311 return 0; 312 313 return omap2_clksel_set_parent(clk, new_parent); 314 } 315 316 /* OMAP3/4 non-CORE DPLL clkops */ 317 318 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 319 320 const struct clkops clkops_omap3_noncore_dpll_ops = { 321 .enable = omap3_noncore_dpll_enable, 322 .disable = omap3_noncore_dpll_disable, 323 }; 324 325 #endif 326 327 328 /*------------------------------------------------------------------------- 329 * Omap2 clock reset and init functions 330 *-------------------------------------------------------------------------*/ 331 332 #ifdef CONFIG_OMAP_RESET_CLOCKS 333 void omap2_clk_disable_unused(struct clk *clk) 334 { 335 u32 regval32, v; 336 337 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 338 339 regval32 = __raw_readl(clk->enable_reg); 340 if ((regval32 & (1 << clk->enable_bit)) == v) 341 return; 342 343 printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); 344 if (cpu_is_omap34xx()) { 345 omap2_clk_enable(clk); 346 omap2_clk_disable(clk); 347 } else 348 _omap2_clk_disable(clk); 349 if (clk->clkdm != NULL) 350 pwrdm_clkdm_state_switch(clk->clkdm); 351 } 352 #endif 353 354 /** 355 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 356 * @mpurate_ck_name: clk name of the clock to change rate 357 * 358 * Change the ARM MPU clock rate to the rate specified on the command 359 * line, if one was specified. @mpurate_ck_name should be 360 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 361 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 362 * handled by the virt_prcm_set clock, but this should be handled by 363 * the OPP layer. XXX This is intended to be handled by the OPP layer 364 * code in the near future and should be removed from the clock code. 365 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 366 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 367 * cannot be found, or 0 upon success. 368 */ 369 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 370 { 371 struct clk *mpurate_ck; 372 int r; 373 374 if (!mpurate) 375 return -EINVAL; 376 377 mpurate_ck = clk_get(NULL, mpurate_ck_name); 378 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 379 return -ENOENT; 380 381 r = clk_set_rate(mpurate_ck, mpurate); 382 if (IS_ERR_VALUE(r)) { 383 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 384 mpurate_ck->name, mpurate, r); 385 return -EINVAL; 386 } 387 388 calibrate_delay(); 389 recalculate_root_clocks(); 390 391 clk_put(mpurate_ck); 392 393 return 0; 394 } 395 396 /** 397 * omap2_clk_print_new_rates - print summary of current clock tree rates 398 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 399 * @core_ck_name: clk name for the on-chip CORE_CLK 400 * @mpu_ck_name: clk name for the ARM MPU clock 401 * 402 * Prints a short message to the console with the HFCLKIN oscillator 403 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 404 * Called by the boot-time MPU rate switching code. XXX This is intended 405 * to be handled by the OPP layer code in the near future and should be 406 * removed from the clock code. No return value. 407 */ 408 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 409 const char *core_ck_name, 410 const char *mpu_ck_name) 411 { 412 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 413 unsigned long hfclkin_rate; 414 415 mpu_ck = clk_get(NULL, mpu_ck_name); 416 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 417 return; 418 419 core_ck = clk_get(NULL, core_ck_name); 420 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 421 return; 422 423 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 424 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 425 return; 426 427 hfclkin_rate = clk_get_rate(hfclkin_ck); 428 429 pr_info("Switched to new clocking rate (Crystal/Core/MPU): " 430 "%ld.%01ld/%ld/%ld MHz\n", 431 (hfclkin_rate / 1000000), 432 ((hfclkin_rate / 100000) % 10), 433 (clk_get_rate(core_ck) / 1000000), 434 (clk_get_rate(mpu_ck) / 1000000)); 435 } 436 437 /* Common data */ 438 439 struct clk_functions omap2_clk_functions = { 440 .clk_enable = omap2_clk_enable, 441 .clk_disable = omap2_clk_disable, 442 .clk_round_rate = omap2_clk_round_rate, 443 .clk_set_rate = omap2_clk_set_rate, 444 .clk_set_parent = omap2_clk_set_parent, 445 .clk_disable_unused = omap2_clk_disable_unused, 446 #ifdef CONFIG_CPU_FREQ 447 /* These will be removed when the OPP code is integrated */ 448 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, 449 .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, 450 #endif 451 }; 452 453