1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/clk-private.h> 27 #include <asm/cpu.h> 28 29 #include <trace/events/power.h> 30 31 #include "soc.h" 32 #include "clockdomain.h" 33 #include "clock.h" 34 #include "cm.h" 35 #include "cm2xxx.h" 36 #include "cm3xxx.h" 37 #include "cm-regbits-24xx.h" 38 #include "cm-regbits-34xx.h" 39 #include "common.h" 40 41 /* 42 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 43 * for a module to indicate that it is no longer in idle 44 */ 45 #define MAX_MODULE_ENABLE_WAIT 100000 46 47 u16 cpu_mask; 48 49 /* 50 * clkdm_control: if true, then when a clock is enabled in the 51 * hardware, its clockdomain will first be enabled; and when a clock 52 * is disabled in the hardware, its clockdomain will be disabled 53 * afterwards. 54 */ 55 static bool clkdm_control = true; 56 57 static LIST_HEAD(clk_hw_omap_clocks); 58 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 59 60 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 61 { 62 if (clk->flags & MEMMAP_ADDRESSING) { 63 struct clk_omap_reg *r = (struct clk_omap_reg *)® 64 writel_relaxed(val, clk_memmaps[r->index] + r->offset); 65 } else { 66 writel_relaxed(val, reg); 67 } 68 } 69 70 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 71 { 72 u32 val; 73 74 if (clk->flags & MEMMAP_ADDRESSING) { 75 struct clk_omap_reg *r = (struct clk_omap_reg *)® 76 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 77 } else { 78 val = readl_relaxed(reg); 79 } 80 81 return val; 82 } 83 84 /* 85 * Used for clocks that have the same value as the parent clock, 86 * divided by some factor 87 */ 88 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 89 unsigned long parent_rate) 90 { 91 struct clk_hw_omap *oclk; 92 93 if (!hw) { 94 pr_warn("%s: hw is NULL\n", __func__); 95 return -EINVAL; 96 } 97 98 oclk = to_clk_hw_omap(hw); 99 100 WARN_ON(!oclk->fixed_div); 101 102 return parent_rate / oclk->fixed_div; 103 } 104 105 /* 106 * OMAP2+ specific clock functions 107 */ 108 109 /* Private functions */ 110 111 112 /** 113 * _wait_idlest_generic - wait for a module to leave the idle state 114 * @reg: virtual address of module IDLEST register 115 * @mask: value to mask against to determine if the module is active 116 * @idlest: idle state indicator (0 or 1) for the clock 117 * @name: name of the clock (for printk) 118 * 119 * Wait for a module to leave idle, where its idle-status register is 120 * not inside the CM module. Returns 1 if the module left idle 121 * promptly, or 0 if the module did not leave idle before the timeout 122 * elapsed. XXX Deprecated - should be moved into drivers for the 123 * individual IP block that the IDLEST register exists in. 124 */ 125 static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, 126 const char *name) 127 { 128 int i = 0, ena = 0; 129 130 ena = (idlest) ? 0 : mask; 131 132 omap_test_timeout(((__raw_readl(reg) & mask) == ena), 133 MAX_MODULE_ENABLE_WAIT, i); 134 135 if (i < MAX_MODULE_ENABLE_WAIT) 136 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 137 name, i); 138 else 139 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 140 name, MAX_MODULE_ENABLE_WAIT); 141 142 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 143 }; 144 145 /** 146 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 147 * @clk: struct clk * belonging to the module 148 * 149 * If the necessary clocks for the OMAP hardware IP block that 150 * corresponds to clock @clk are enabled, then wait for the module to 151 * indicate readiness (i.e., to leave IDLE). This code does not 152 * belong in the clock code and will be moved in the medium term to 153 * module-dependent code. No return value. 154 */ 155 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 156 { 157 void __iomem *companion_reg, *idlest_reg; 158 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 159 s16 prcm_mod; 160 int r; 161 162 /* Not all modules have multiple clocks that their IDLEST depends on */ 163 if (clk->ops->find_companion) { 164 clk->ops->find_companion(clk, &companion_reg, &other_bit); 165 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 166 return; 167 } 168 169 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 170 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 171 if (r) { 172 /* IDLEST register not in the CM module */ 173 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, 174 __clk_get_name(clk->hw.clk)); 175 } else { 176 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 177 }; 178 } 179 180 /* Public functions */ 181 182 /** 183 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 184 * @clk: OMAP clock struct ptr to use 185 * 186 * Convert a clockdomain name stored in a struct clk 'clk' into a 187 * clockdomain pointer, and save it into the struct clk. Intended to be 188 * called during clk_register(). No return value. 189 */ 190 void omap2_init_clk_clkdm(struct clk_hw *hw) 191 { 192 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 193 struct clockdomain *clkdm; 194 const char *clk_name; 195 196 if (!clk->clkdm_name) 197 return; 198 199 clk_name = __clk_get_name(hw->clk); 200 201 clkdm = clkdm_lookup(clk->clkdm_name); 202 if (clkdm) { 203 pr_debug("clock: associated clk %s to clkdm %s\n", 204 clk_name, clk->clkdm_name); 205 clk->clkdm = clkdm; 206 } else { 207 pr_debug("clock: could not associate clk %s to clkdm %s\n", 208 clk_name, clk->clkdm_name); 209 } 210 } 211 212 /** 213 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 214 * 215 * Prevent the OMAP clock code from calling into the clockdomain code 216 * when a hardware clock in that clockdomain is enabled or disabled. 217 * Intended to be called at init time from omap*_clk_init(). No 218 * return value. 219 */ 220 void __init omap2_clk_disable_clkdm_control(void) 221 { 222 clkdm_control = false; 223 } 224 225 /** 226 * omap2_clk_dflt_find_companion - find companion clock to @clk 227 * @clk: struct clk * to find the companion clock of 228 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 229 * @other_bit: u8 ** to return the companion clock bit shift in 230 * 231 * Note: We don't need special code here for INVERT_ENABLE for the 232 * time being since INVERT_ENABLE only applies to clocks enabled by 233 * CM_CLKEN_PLL 234 * 235 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 236 * just a matter of XORing the bits. 237 * 238 * Some clocks don't have companion clocks. For example, modules with 239 * only an interface clock (such as MAILBOXES) don't have a companion 240 * clock. Right now, this code relies on the hardware exporting a bit 241 * in the correct companion register that indicates that the 242 * nonexistent 'companion clock' is active. Future patches will 243 * associate this type of code with per-module data structures to 244 * avoid this issue, and remove the casts. No return value. 245 */ 246 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 247 void __iomem **other_reg, u8 *other_bit) 248 { 249 u32 r; 250 251 /* 252 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 253 * it's just a matter of XORing the bits. 254 */ 255 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 256 257 *other_reg = (__force void __iomem *)r; 258 *other_bit = clk->enable_bit; 259 } 260 261 /** 262 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 263 * @clk: struct clk * to find IDLEST info for 264 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 265 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 266 * @idlest_val: u8 * to return the idle status indicator 267 * 268 * Return the CM_IDLEST register address and bit shift corresponding 269 * to the module that "owns" this clock. This default code assumes 270 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 271 * the IDLEST register address ID corresponds to the CM_*CLKEN 272 * register address ID (e.g., that CM_FCLKEN2 corresponds to 273 * CM_IDLEST2). This is not true for all modules. No return value. 274 */ 275 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 276 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 277 { 278 u32 r; 279 280 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 281 *idlest_reg = (__force void __iomem *)r; 282 *idlest_bit = clk->enable_bit; 283 284 /* 285 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 286 * 34xx reverses this, just to keep us on our toes 287 * AM35xx uses both, depending on the module. 288 */ 289 if (cpu_is_omap24xx()) 290 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 291 else if (cpu_is_omap34xx()) 292 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 293 else 294 BUG(); 295 296 } 297 298 /** 299 * omap2_dflt_clk_enable - enable a clock in the hardware 300 * @hw: struct clk_hw * of the clock to enable 301 * 302 * Enable the clock @hw in the hardware. We first call into the OMAP 303 * clockdomain code to "enable" the corresponding clockdomain if this 304 * is the first enabled user of the clockdomain. Then program the 305 * hardware to enable the clock. Then wait for the IP block that uses 306 * this clock to leave idle (if applicable). Returns the error value 307 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 308 * if @hw has a null clock enable_reg, or zero upon success. 309 */ 310 int omap2_dflt_clk_enable(struct clk_hw *hw) 311 { 312 struct clk_hw_omap *clk; 313 u32 v; 314 int ret = 0; 315 316 clk = to_clk_hw_omap(hw); 317 318 if (clkdm_control && clk->clkdm) { 319 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 320 if (ret) { 321 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", 322 __func__, __clk_get_name(hw->clk), 323 clk->clkdm->name, ret); 324 return ret; 325 } 326 } 327 328 if (unlikely(clk->enable_reg == NULL)) { 329 pr_err("%s: %s missing enable_reg\n", __func__, 330 __clk_get_name(hw->clk)); 331 ret = -EINVAL; 332 goto err; 333 } 334 335 /* FIXME should not have INVERT_ENABLE bit here */ 336 v = __raw_readl(clk->enable_reg); 337 if (clk->flags & INVERT_ENABLE) 338 v &= ~(1 << clk->enable_bit); 339 else 340 v |= (1 << clk->enable_bit); 341 __raw_writel(v, clk->enable_reg); 342 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 343 344 if (clk->ops && clk->ops->find_idlest) 345 _omap2_module_wait_ready(clk); 346 347 return 0; 348 349 err: 350 if (clkdm_control && clk->clkdm) 351 clkdm_clk_disable(clk->clkdm, hw->clk); 352 return ret; 353 } 354 355 /** 356 * omap2_dflt_clk_disable - disable a clock in the hardware 357 * @hw: struct clk_hw * of the clock to disable 358 * 359 * Disable the clock @hw in the hardware, and call into the OMAP 360 * clockdomain code to "disable" the corresponding clockdomain if all 361 * clocks/hwmods in that clockdomain are now disabled. No return 362 * value. 363 */ 364 void omap2_dflt_clk_disable(struct clk_hw *hw) 365 { 366 struct clk_hw_omap *clk; 367 u32 v; 368 369 clk = to_clk_hw_omap(hw); 370 if (!clk->enable_reg) { 371 /* 372 * 'independent' here refers to a clock which is not 373 * controlled by its parent. 374 */ 375 pr_err("%s: independent clock %s has no enable_reg\n", 376 __func__, __clk_get_name(hw->clk)); 377 return; 378 } 379 380 v = __raw_readl(clk->enable_reg); 381 if (clk->flags & INVERT_ENABLE) 382 v |= (1 << clk->enable_bit); 383 else 384 v &= ~(1 << clk->enable_bit); 385 __raw_writel(v, clk->enable_reg); 386 /* No OCP barrier needed here since it is a disable operation */ 387 388 if (clkdm_control && clk->clkdm) 389 clkdm_clk_disable(clk->clkdm, hw->clk); 390 } 391 392 /** 393 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw 394 * @hw: struct clk_hw * of the clock being enabled 395 * 396 * Increment the usecount of the clockdomain of the clock pointed to 397 * by @hw; if the usecount is 1, the clockdomain will be "enabled." 398 * Only needed for clocks that don't use omap2_dflt_clk_enable() as 399 * their enable function pointer. Passes along the return value of 400 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a 401 * clockdomain, or 0 if clock framework-based clockdomain control is 402 * not implemented. 403 */ 404 int omap2_clkops_enable_clkdm(struct clk_hw *hw) 405 { 406 struct clk_hw_omap *clk; 407 int ret = 0; 408 409 clk = to_clk_hw_omap(hw); 410 411 if (unlikely(!clk->clkdm)) { 412 pr_err("%s: %s: no clkdm set ?!\n", __func__, 413 __clk_get_name(hw->clk)); 414 return -EINVAL; 415 } 416 417 if (unlikely(clk->enable_reg)) 418 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 419 __clk_get_name(hw->clk)); 420 421 if (!clkdm_control) { 422 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 423 __func__, __clk_get_name(hw->clk)); 424 return 0; 425 } 426 427 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 428 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 429 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); 430 431 return ret; 432 } 433 434 /** 435 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw 436 * @hw: struct clk_hw * of the clock being disabled 437 * 438 * Decrement the usecount of the clockdomain of the clock pointed to 439 * by @hw; if the usecount is 0, the clockdomain will be "disabled." 440 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their 441 * disable function pointer. No return value. 442 */ 443 void omap2_clkops_disable_clkdm(struct clk_hw *hw) 444 { 445 struct clk_hw_omap *clk; 446 447 clk = to_clk_hw_omap(hw); 448 449 if (unlikely(!clk->clkdm)) { 450 pr_err("%s: %s: no clkdm set ?!\n", __func__, 451 __clk_get_name(hw->clk)); 452 return; 453 } 454 455 if (unlikely(clk->enable_reg)) 456 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 457 __clk_get_name(hw->clk)); 458 459 if (!clkdm_control) { 460 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 461 __func__, __clk_get_name(hw->clk)); 462 return; 463 } 464 465 clkdm_clk_disable(clk->clkdm, hw->clk); 466 } 467 468 /** 469 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 470 * @hw: struct clk_hw * to check 471 * 472 * Return 1 if the clock represented by @hw is enabled in the 473 * hardware, or 0 otherwise. Intended for use in the struct 474 * clk_ops.is_enabled function pointer. 475 */ 476 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 477 { 478 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 479 u32 v; 480 481 v = __raw_readl(clk->enable_reg); 482 483 if (clk->flags & INVERT_ENABLE) 484 v ^= BIT(clk->enable_bit); 485 486 v &= BIT(clk->enable_bit); 487 488 return v ? 1 : 0; 489 } 490 491 static int __initdata mpurate; 492 493 /* 494 * By default we use the rate set by the bootloader. 495 * You can override this with mpurate= cmdline option. 496 */ 497 static int __init omap_clk_setup(char *str) 498 { 499 get_option(&str, &mpurate); 500 501 if (!mpurate) 502 return 1; 503 504 if (mpurate < 1000) 505 mpurate *= 1000000; 506 507 return 1; 508 } 509 __setup("mpurate=", omap_clk_setup); 510 511 /** 512 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock 513 * @clk: struct clk * to initialize 514 * 515 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used 516 * temporarily for autoidle handling, until this support can be 517 * integrated into the common clock framework code in some way. No 518 * return value. 519 */ 520 void omap2_init_clk_hw_omap_clocks(struct clk *clk) 521 { 522 struct clk_hw_omap *c; 523 524 if (__clk_get_flags(clk) & CLK_IS_BASIC) 525 return; 526 527 c = to_clk_hw_omap(__clk_get_hw(clk)); 528 list_add(&c->node, &clk_hw_omap_clocks); 529 } 530 531 /** 532 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that 533 * support it 534 * 535 * Enable clock autoidle on all OMAP clocks that have allow_idle 536 * function pointers associated with them. This function is intended 537 * to be temporary until support for this is added to the common clock 538 * code. Returns 0. 539 */ 540 int omap2_clk_enable_autoidle_all(void) 541 { 542 struct clk_hw_omap *c; 543 544 list_for_each_entry(c, &clk_hw_omap_clocks, node) 545 if (c->ops && c->ops->allow_idle) 546 c->ops->allow_idle(c); 547 548 of_ti_clk_allow_autoidle_all(); 549 550 return 0; 551 } 552 553 /** 554 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that 555 * support it 556 * 557 * Disable clock autoidle on all OMAP clocks that have allow_idle 558 * function pointers associated with them. This function is intended 559 * to be temporary until support for this is added to the common clock 560 * code. Returns 0. 561 */ 562 int omap2_clk_disable_autoidle_all(void) 563 { 564 struct clk_hw_omap *c; 565 566 list_for_each_entry(c, &clk_hw_omap_clocks, node) 567 if (c->ops && c->ops->deny_idle) 568 c->ops->deny_idle(c); 569 570 of_ti_clk_deny_autoidle_all(); 571 572 return 0; 573 } 574 575 /** 576 * omap2_clk_deny_idle - disable autoidle on an OMAP clock 577 * @clk: struct clk * to disable autoidle for 578 * 579 * Disable autoidle on an OMAP clock. 580 */ 581 int omap2_clk_deny_idle(struct clk *clk) 582 { 583 struct clk_hw_omap *c; 584 585 if (__clk_get_flags(clk) & CLK_IS_BASIC) 586 return -EINVAL; 587 588 c = to_clk_hw_omap(__clk_get_hw(clk)); 589 if (c->ops && c->ops->deny_idle) 590 c->ops->deny_idle(c); 591 return 0; 592 } 593 594 /** 595 * omap2_clk_allow_idle - enable autoidle on an OMAP clock 596 * @clk: struct clk * to enable autoidle for 597 * 598 * Enable autoidle on an OMAP clock. 599 */ 600 int omap2_clk_allow_idle(struct clk *clk) 601 { 602 struct clk_hw_omap *c; 603 604 if (__clk_get_flags(clk) & CLK_IS_BASIC) 605 return -EINVAL; 606 607 c = to_clk_hw_omap(__clk_get_hw(clk)); 608 if (c->ops && c->ops->allow_idle) 609 c->ops->allow_idle(c); 610 return 0; 611 } 612 613 /** 614 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 615 * @clk_names: ptr to an array of strings of clock names to enable 616 * @num_clocks: number of clock names in @clk_names 617 * 618 * Prepare and enable a list of clocks, named by @clk_names. No 619 * return value. XXX Deprecated; only needed until these clocks are 620 * properly claimed and enabled by the drivers or core code that uses 621 * them. XXX What code disables & calls clk_put on these clocks? 622 */ 623 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) 624 { 625 struct clk *init_clk; 626 int i; 627 628 for (i = 0; i < num_clocks; i++) { 629 init_clk = clk_get(NULL, clk_names[i]); 630 clk_prepare_enable(init_clk); 631 } 632 } 633 634 const struct clk_hw_omap_ops clkhwops_wait = { 635 .find_idlest = omap2_clk_dflt_find_idlest, 636 .find_companion = omap2_clk_dflt_find_companion, 637 }; 638 639 /** 640 * omap_clocks_register - register an array of omap_clk 641 * @ocs: pointer to an array of omap_clk to register 642 */ 643 void __init omap_clocks_register(struct omap_clk oclks[], int cnt) 644 { 645 struct omap_clk *c; 646 647 for (c = oclks; c < oclks + cnt; c++) { 648 clkdev_add(&c->lk); 649 if (!__clk_init(NULL, c->lk.clk)) 650 omap2_init_clk_hw_omap_clocks(c->lk.clk); 651 } 652 } 653 654 /** 655 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 656 * @mpurate_ck_name: clk name of the clock to change rate 657 * 658 * Change the ARM MPU clock rate to the rate specified on the command 659 * line, if one was specified. @mpurate_ck_name should be 660 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 661 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 662 * handled by the virt_prcm_set clock, but this should be handled by 663 * the OPP layer. XXX This is intended to be handled by the OPP layer 664 * code in the near future and should be removed from the clock code. 665 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 666 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 667 * cannot be found, or 0 upon success. 668 */ 669 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 670 { 671 struct clk *mpurate_ck; 672 int r; 673 674 if (!mpurate) 675 return -EINVAL; 676 677 mpurate_ck = clk_get(NULL, mpurate_ck_name); 678 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 679 return -ENOENT; 680 681 r = clk_set_rate(mpurate_ck, mpurate); 682 if (r < 0) { 683 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 684 mpurate_ck_name, mpurate, r); 685 clk_put(mpurate_ck); 686 return -EINVAL; 687 } 688 689 calibrate_delay(); 690 clk_put(mpurate_ck); 691 692 return 0; 693 } 694 695 /** 696 * omap2_clk_print_new_rates - print summary of current clock tree rates 697 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 698 * @core_ck_name: clk name for the on-chip CORE_CLK 699 * @mpu_ck_name: clk name for the ARM MPU clock 700 * 701 * Prints a short message to the console with the HFCLKIN oscillator 702 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 703 * Called by the boot-time MPU rate switching code. XXX This is intended 704 * to be handled by the OPP layer code in the near future and should be 705 * removed from the clock code. No return value. 706 */ 707 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 708 const char *core_ck_name, 709 const char *mpu_ck_name) 710 { 711 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 712 unsigned long hfclkin_rate; 713 714 mpu_ck = clk_get(NULL, mpu_ck_name); 715 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 716 return; 717 718 core_ck = clk_get(NULL, core_ck_name); 719 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 720 return; 721 722 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 723 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 724 return; 725 726 hfclkin_rate = clk_get_rate(hfclkin_ck); 727 728 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 729 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 730 (clk_get_rate(core_ck) / 1000000), 731 (clk_get_rate(mpu_ck) / 1000000)); 732 } 733