1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <asm/bitops.h> 25 26 #include <asm/io.h> 27 28 #include <asm/arch/clock.h> 29 #include <asm/arch/sram.h> 30 #include <asm/arch/cpu.h> 31 #include <asm/div64.h> 32 33 #include "memory.h" 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 #define MAX_CLOCK_ENABLE_WAIT 100000 43 44 u8 cpu_mask; 45 46 /*------------------------------------------------------------------------- 47 * Omap2 specific clock functions 48 *-------------------------------------------------------------------------*/ 49 50 /** 51 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 52 * @clk: OMAP clock struct ptr to use 53 * 54 * Given a pointer to a source-selectable struct clk, read the hardware 55 * register and determine what its parent is currently set to. Update the 56 * clk->parent field with the appropriate clk ptr. 57 */ 58 void omap2_init_clksel_parent(struct clk *clk) 59 { 60 const struct clksel *clks; 61 const struct clksel_rate *clkr; 62 u32 r, found = 0; 63 64 if (!clk->clksel) 65 return; 66 67 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 68 r >>= __ffs(clk->clksel_mask); 69 70 for (clks = clk->clksel; clks->parent && !found; clks++) { 71 for (clkr = clks->rates; clkr->div && !found; clkr++) { 72 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 73 if (clk->parent != clks->parent) { 74 pr_debug("clock: inited %s parent " 75 "to %s (was %s)\n", 76 clk->name, clks->parent->name, 77 ((clk->parent) ? 78 clk->parent->name : "NULL")); 79 clk->parent = clks->parent; 80 }; 81 found = 1; 82 } 83 } 84 } 85 86 if (!found) 87 printk(KERN_ERR "clock: init parent: could not find " 88 "regval %0x for clock %s\n", r, clk->name); 89 90 return; 91 } 92 93 /* Returns the DPLL rate */ 94 u32 omap2_get_dpll_rate(struct clk *clk) 95 { 96 long long dpll_clk; 97 u32 dpll_mult, dpll_div, dpll; 98 const struct dpll_data *dd; 99 100 dd = clk->dpll_data; 101 /* REVISIT: What do we return on error? */ 102 if (!dd) 103 return 0; 104 105 dpll = __raw_readl(dd->mult_div1_reg); 106 dpll_mult = dpll & dd->mult_mask; 107 dpll_mult >>= __ffs(dd->mult_mask); 108 dpll_div = dpll & dd->div1_mask; 109 dpll_div >>= __ffs(dd->div1_mask); 110 111 dpll_clk = (long long)clk->parent->rate * dpll_mult; 112 do_div(dpll_clk, dpll_div + 1); 113 114 return dpll_clk; 115 } 116 117 /* 118 * Used for clocks that have the same value as the parent clock, 119 * divided by some factor 120 */ 121 void omap2_fixed_divisor_recalc(struct clk *clk) 122 { 123 WARN_ON(!clk->fixed_div); 124 125 clk->rate = clk->parent->rate / clk->fixed_div; 126 127 if (clk->flags & RATE_PROPAGATES) 128 propagate_rate(clk); 129 } 130 131 /** 132 * omap2_wait_clock_ready - wait for clock to enable 133 * @reg: physical address of clock IDLEST register 134 * @mask: value to mask against to determine if the clock is active 135 * @name: name of the clock (for printk) 136 * 137 * Returns 1 if the clock enabled in time, or 0 if it failed to enable 138 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. 139 */ 140 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) 141 { 142 int i = 0; 143 int ena = 0; 144 145 /* 146 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 147 * 34xx reverses this, just to keep us on our toes 148 */ 149 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { 150 ena = mask; 151 } else if (cpu_mask & RATE_IN_343X) { 152 ena = 0; 153 } 154 155 /* Wait for lock */ 156 while (((__raw_readl(reg) & mask) != ena) && 157 (i++ < MAX_CLOCK_ENABLE_WAIT)) { 158 udelay(1); 159 } 160 161 if (i < MAX_CLOCK_ENABLE_WAIT) 162 pr_debug("Clock %s stable after %d loops\n", name, i); 163 else 164 printk(KERN_ERR "Clock %s didn't enable in %d tries\n", 165 name, MAX_CLOCK_ENABLE_WAIT); 166 167 168 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; 169 }; 170 171 172 /* 173 * Note: We don't need special code here for INVERT_ENABLE 174 * for the time being since INVERT_ENABLE only applies to clocks enabled by 175 * CM_CLKEN_PLL 176 */ 177 static void omap2_clk_wait_ready(struct clk *clk) 178 { 179 void __iomem *reg, *other_reg, *st_reg; 180 u32 bit; 181 182 /* 183 * REVISIT: This code is pretty ugly. It would be nice to generalize 184 * it and pull it into struct clk itself somehow. 185 */ 186 reg = clk->enable_reg; 187 if ((((u32)reg & 0xff) >= CM_FCLKEN1) && 188 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) 189 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ 190 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && 191 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) 192 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ 193 else 194 return; 195 196 /* REVISIT: What are the appropriate exclusions for 34XX? */ 197 /* No check for DSS or cam clocks */ 198 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ 199 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || 200 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || 201 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) 202 return; 203 } 204 205 /* REVISIT: What are the appropriate exclusions for 34XX? */ 206 /* OMAP3: ignore DSS-mod clocks */ 207 if (cpu_is_omap34xx() && 208 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0))) 209 return; 210 211 /* Check if both functional and interface clocks 212 * are running. */ 213 bit = 1 << clk->enable_bit; 214 if (!(__raw_readl(other_reg) & bit)) 215 return; 216 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ 217 218 omap2_wait_clock_ready(st_reg, bit, clk->name); 219 } 220 221 /* Enables clock without considering parent dependencies or use count 222 * REVISIT: Maybe change this to use clk->enable like on omap1? 223 */ 224 int _omap2_clk_enable(struct clk *clk) 225 { 226 u32 regval32; 227 228 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) 229 return 0; 230 231 if (clk->enable) 232 return clk->enable(clk); 233 234 if (unlikely(clk->enable_reg == 0)) { 235 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 236 clk->name); 237 return 0; /* REVISIT: -EINVAL */ 238 } 239 240 regval32 = __raw_readl(clk->enable_reg); 241 if (clk->flags & INVERT_ENABLE) 242 regval32 &= ~(1 << clk->enable_bit); 243 else 244 regval32 |= (1 << clk->enable_bit); 245 __raw_writel(regval32, clk->enable_reg); 246 wmb(); 247 248 omap2_clk_wait_ready(clk); 249 250 return 0; 251 } 252 253 /* Disables clock without considering parent dependencies or use count */ 254 void _omap2_clk_disable(struct clk *clk) 255 { 256 u32 regval32; 257 258 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) 259 return; 260 261 if (clk->disable) { 262 clk->disable(clk); 263 return; 264 } 265 266 if (clk->enable_reg == 0) { 267 /* 268 * 'Independent' here refers to a clock which is not 269 * controlled by its parent. 270 */ 271 printk(KERN_ERR "clock: clk_disable called on independent " 272 "clock %s which has no enable_reg\n", clk->name); 273 return; 274 } 275 276 regval32 = __raw_readl(clk->enable_reg); 277 if (clk->flags & INVERT_ENABLE) 278 regval32 |= (1 << clk->enable_bit); 279 else 280 regval32 &= ~(1 << clk->enable_bit); 281 __raw_writel(regval32, clk->enable_reg); 282 wmb(); 283 } 284 285 void omap2_clk_disable(struct clk *clk) 286 { 287 if (clk->usecount > 0 && !(--clk->usecount)) { 288 _omap2_clk_disable(clk); 289 if (likely((u32)clk->parent)) 290 omap2_clk_disable(clk->parent); 291 } 292 } 293 294 int omap2_clk_enable(struct clk *clk) 295 { 296 int ret = 0; 297 298 if (clk->usecount++ == 0) { 299 if (likely((u32)clk->parent)) 300 ret = omap2_clk_enable(clk->parent); 301 302 if (unlikely(ret != 0)) { 303 clk->usecount--; 304 return ret; 305 } 306 307 ret = _omap2_clk_enable(clk); 308 309 if (unlikely(ret != 0) && clk->parent) { 310 omap2_clk_disable(clk->parent); 311 clk->usecount--; 312 } 313 } 314 315 return ret; 316 } 317 318 /* 319 * Used for clocks that are part of CLKSEL_xyz governed clocks. 320 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 321 */ 322 void omap2_clksel_recalc(struct clk *clk) 323 { 324 u32 div = 0; 325 326 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 327 328 div = omap2_clksel_get_divisor(clk); 329 if (div == 0) 330 return; 331 332 if (unlikely(clk->rate == clk->parent->rate / div)) 333 return; 334 clk->rate = clk->parent->rate / div; 335 336 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); 337 338 if (unlikely(clk->flags & RATE_PROPAGATES)) 339 propagate_rate(clk); 340 } 341 342 /** 343 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 344 * @clk: OMAP struct clk ptr to inspect 345 * @src_clk: OMAP struct clk ptr of the parent clk to search for 346 * 347 * Scan the struct clksel array associated with the clock to find 348 * the element associated with the supplied parent clock address. 349 * Returns a pointer to the struct clksel on success or NULL on error. 350 */ 351 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 352 struct clk *src_clk) 353 { 354 const struct clksel *clks; 355 356 if (!clk->clksel) 357 return NULL; 358 359 for (clks = clk->clksel; clks->parent; clks++) { 360 if (clks->parent == src_clk) 361 break; /* Found the requested parent */ 362 } 363 364 if (!clks->parent) { 365 printk(KERN_ERR "clock: Could not find parent clock %s in " 366 "clksel array of clock %s\n", src_clk->name, 367 clk->name); 368 return NULL; 369 } 370 371 return clks; 372 } 373 374 /** 375 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 376 * @clk: OMAP struct clk to use 377 * @target_rate: desired clock rate 378 * @new_div: ptr to where we should store the divisor 379 * 380 * Finds 'best' divider value in an array based on the source and target 381 * rates. The divider array must be sorted with smallest divider first. 382 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 383 * they are only settable as part of virtual_prcm set. 384 * 385 * Returns the rounded clock rate or returns 0xffffffff on error. 386 */ 387 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 388 u32 *new_div) 389 { 390 unsigned long test_rate; 391 const struct clksel *clks; 392 const struct clksel_rate *clkr; 393 u32 last_div = 0; 394 395 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", 396 clk->name, target_rate); 397 398 *new_div = 1; 399 400 clks = omap2_get_clksel_by_parent(clk, clk->parent); 401 if (clks == NULL) 402 return ~0; 403 404 for (clkr = clks->rates; clkr->div; clkr++) { 405 if (!(clkr->flags & cpu_mask)) 406 continue; 407 408 /* Sanity check */ 409 if (clkr->div <= last_div) 410 printk(KERN_ERR "clock: clksel_rate table not sorted " 411 "for clock %s", clk->name); 412 413 last_div = clkr->div; 414 415 test_rate = clk->parent->rate / clkr->div; 416 417 if (test_rate <= target_rate) 418 break; /* found it */ 419 } 420 421 if (!clkr->div) { 422 printk(KERN_ERR "clock: Could not find divisor for target " 423 "rate %ld for clock %s parent %s\n", target_rate, 424 clk->name, clk->parent->name); 425 return ~0; 426 } 427 428 *new_div = clkr->div; 429 430 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, 431 (clk->parent->rate / clkr->div)); 432 433 return (clk->parent->rate / clkr->div); 434 } 435 436 /** 437 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 438 * @clk: OMAP struct clk to use 439 * @target_rate: desired clock rate 440 * 441 * Compatibility wrapper for OMAP clock framework 442 * Finds best target rate based on the source clock and possible dividers. 443 * rates. The divider array must be sorted with smallest divider first. 444 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 445 * they are only settable as part of virtual_prcm set. 446 * 447 * Returns the rounded clock rate or returns 0xffffffff on error. 448 */ 449 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 450 { 451 u32 new_div; 452 453 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 454 } 455 456 457 /* Given a clock and a rate apply a clock specific rounding function */ 458 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 459 { 460 if (clk->round_rate != 0) 461 return clk->round_rate(clk, rate); 462 463 if (clk->flags & RATE_FIXED) 464 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 465 "on fixed-rate clock %s\n", clk->name); 466 467 return clk->rate; 468 } 469 470 /** 471 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 472 * @clk: OMAP struct clk to use 473 * @field_val: register field value to find 474 * 475 * Given a struct clk of a rate-selectable clksel clock, and a register field 476 * value to search for, find the corresponding clock divisor. The register 477 * field value should be pre-masked and shifted down so the LSB is at bit 0 478 * before calling. Returns 0 on error 479 */ 480 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 481 { 482 const struct clksel *clks; 483 const struct clksel_rate *clkr; 484 485 clks = omap2_get_clksel_by_parent(clk, clk->parent); 486 if (clks == NULL) 487 return 0; 488 489 for (clkr = clks->rates; clkr->div; clkr++) { 490 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 491 break; 492 } 493 494 if (!clkr->div) { 495 printk(KERN_ERR "clock: Could not find fieldval %d for " 496 "clock %s parent %s\n", field_val, clk->name, 497 clk->parent->name); 498 return 0; 499 } 500 501 return clkr->div; 502 } 503 504 /** 505 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 506 * @clk: OMAP struct clk to use 507 * @div: integer divisor to search for 508 * 509 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 510 * find the corresponding register field value. The return register value is 511 * the value before left-shifting. Returns 0xffffffff on error 512 */ 513 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 514 { 515 const struct clksel *clks; 516 const struct clksel_rate *clkr; 517 518 /* should never happen */ 519 WARN_ON(div == 0); 520 521 clks = omap2_get_clksel_by_parent(clk, clk->parent); 522 if (clks == NULL) 523 return 0; 524 525 for (clkr = clks->rates; clkr->div; clkr++) { 526 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 527 break; 528 } 529 530 if (!clkr->div) { 531 printk(KERN_ERR "clock: Could not find divisor %d for " 532 "clock %s parent %s\n", div, clk->name, 533 clk->parent->name); 534 return 0; 535 } 536 537 return clkr->val; 538 } 539 540 /** 541 * omap2_get_clksel - find clksel register addr & field mask for a clk 542 * @clk: struct clk to use 543 * @field_mask: ptr to u32 to store the register field mask 544 * 545 * Returns the address of the clksel register upon success or NULL on error. 546 */ 547 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 548 { 549 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0))) 550 return NULL; 551 552 *field_mask = clk->clksel_mask; 553 554 return clk->clksel_reg; 555 } 556 557 /** 558 * omap2_clksel_get_divisor - get current divider applied to parent clock. 559 * @clk: OMAP struct clk to use. 560 * 561 * Returns the integer divisor upon success or 0 on error. 562 */ 563 u32 omap2_clksel_get_divisor(struct clk *clk) 564 { 565 u32 field_mask, field_val; 566 void __iomem *div_addr; 567 568 div_addr = omap2_get_clksel(clk, &field_mask); 569 if (div_addr == 0) 570 return 0; 571 572 field_val = __raw_readl(div_addr) & field_mask; 573 field_val >>= __ffs(field_mask); 574 575 return omap2_clksel_to_divisor(clk, field_val); 576 } 577 578 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 579 { 580 u32 field_mask, field_val, reg_val, validrate, new_div = 0; 581 void __iomem *div_addr; 582 583 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 584 if (validrate != rate) 585 return -EINVAL; 586 587 div_addr = omap2_get_clksel(clk, &field_mask); 588 if (div_addr == 0) 589 return -EINVAL; 590 591 field_val = omap2_divisor_to_clksel(clk, new_div); 592 if (field_val == ~0) 593 return -EINVAL; 594 595 reg_val = __raw_readl(div_addr); 596 reg_val &= ~field_mask; 597 reg_val |= (field_val << __ffs(field_mask)); 598 __raw_writel(reg_val, div_addr); 599 wmb(); 600 601 clk->rate = clk->parent->rate / new_div; 602 603 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 604 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 605 wmb(); 606 } 607 608 return 0; 609 } 610 611 612 /* Set the clock rate for a clock source */ 613 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 614 { 615 int ret = -EINVAL; 616 617 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 618 619 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 620 rate table mechanism, driven by mpu_speed */ 621 if (clk->flags & CONFIG_PARTICIPANT) 622 return -EINVAL; 623 624 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 625 if (clk->set_rate != 0) 626 ret = clk->set_rate(clk, rate); 627 628 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 629 propagate_rate(clk); 630 631 return ret; 632 } 633 634 /* 635 * Converts encoded control register address into a full address 636 * On error, *src_addr will be returned as 0. 637 */ 638 static u32 omap2_clksel_get_src_field(void __iomem **src_addr, 639 struct clk *src_clk, u32 *field_mask, 640 struct clk *clk, u32 *parent_div) 641 { 642 const struct clksel *clks; 643 const struct clksel_rate *clkr; 644 645 *parent_div = 0; 646 *src_addr = 0; 647 648 clks = omap2_get_clksel_by_parent(clk, src_clk); 649 if (clks == NULL) 650 return 0; 651 652 for (clkr = clks->rates; clkr->div; clkr++) { 653 if (clkr->flags & (cpu_mask | DEFAULT_RATE)) 654 break; /* Found the default rate for this platform */ 655 } 656 657 if (!clkr->div) { 658 printk(KERN_ERR "clock: Could not find default rate for " 659 "clock %s parent %s\n", clk->name, 660 src_clk->parent->name); 661 return 0; 662 } 663 664 /* Should never happen. Add a clksel mask to the struct clk. */ 665 WARN_ON(clk->clksel_mask == 0); 666 667 *field_mask = clk->clksel_mask; 668 *src_addr = clk->clksel_reg; 669 *parent_div = clkr->div; 670 671 return clkr->val; 672 } 673 674 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 675 { 676 void __iomem *src_addr; 677 u32 field_val, field_mask, reg_val, parent_div; 678 679 if (unlikely(clk->flags & CONFIG_PARTICIPANT)) 680 return -EINVAL; 681 682 if (!clk->clksel) 683 return -EINVAL; 684 685 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 686 &field_mask, clk, &parent_div); 687 if (src_addr == 0) 688 return -EINVAL; 689 690 if (clk->usecount > 0) 691 _omap2_clk_disable(clk); 692 693 /* Set new source value (previous dividers if any in effect) */ 694 reg_val = __raw_readl(src_addr) & ~field_mask; 695 reg_val |= (field_val << __ffs(field_mask)); 696 __raw_writel(reg_val, src_addr); 697 wmb(); 698 699 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 700 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 701 wmb(); 702 } 703 704 if (clk->usecount > 0) 705 _omap2_clk_enable(clk); 706 707 clk->parent = new_parent; 708 709 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 710 clk->rate = new_parent->rate; 711 712 if (parent_div > 0) 713 clk->rate /= parent_div; 714 715 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 716 clk->name, clk->parent->name, clk->rate); 717 718 if (unlikely(clk->flags & RATE_PROPAGATES)) 719 propagate_rate(clk); 720 721 return 0; 722 } 723 724 /*------------------------------------------------------------------------- 725 * Omap2 clock reset and init functions 726 *-------------------------------------------------------------------------*/ 727 728 #ifdef CONFIG_OMAP_RESET_CLOCKS 729 void omap2_clk_disable_unused(struct clk *clk) 730 { 731 u32 regval32, v; 732 733 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 734 735 regval32 = __raw_readl(clk->enable_reg); 736 if ((regval32 & (1 << clk->enable_bit)) == v) 737 return; 738 739 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 740 _omap2_clk_disable(clk); 741 } 742 #endif 743