1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/io.h> 26 #include <linux/bitops.h> 27 #include <linux/of_address.h> 28 #include <asm/cpu.h> 29 30 #include <trace/events/power.h> 31 32 #include "soc.h" 33 #include "clockdomain.h" 34 #include "clock.h" 35 #include "cm.h" 36 #include "cm2xxx.h" 37 #include "cm3xxx.h" 38 #include "cm-regbits-24xx.h" 39 #include "cm-regbits-34xx.h" 40 #include "common.h" 41 42 u16 cpu_mask; 43 44 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 45 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 46 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 47 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 48 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 49 50 /* 51 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. 52 * From device data manual section 4.3 "DPLL and DLL Specifications". 53 */ 54 #define OMAP3PLUS_DPLL_FINT_MIN 32000 55 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 56 57 static struct ti_clk_ll_ops omap_clk_ll_ops = { 58 .clkdm_clk_enable = clkdm_clk_enable, 59 .clkdm_clk_disable = clkdm_clk_disable, 60 .clkdm_lookup = clkdm_lookup, 61 .cm_wait_module_ready = omap_cm_wait_module_ready, 62 .cm_split_idlest_reg = cm_split_idlest_reg, 63 }; 64 65 /** 66 * omap2_clk_setup_ll_ops - setup clock driver low-level ops 67 * 68 * Sets up clock driver low-level platform ops. These are needed 69 * for register accesses and various other misc platform operations. 70 * Returns 0 on success, -EBUSY if low level ops have been registered 71 * already. 72 */ 73 int __init omap2_clk_setup_ll_ops(void) 74 { 75 return ti_clk_setup_ll_ops(&omap_clk_ll_ops); 76 } 77 78 /* 79 * OMAP2+ specific clock functions 80 */ 81 82 /** 83 * ti_clk_init_features - init clock features struct for the SoC 84 * 85 * Initializes the clock features struct based on the SoC type. 86 */ 87 void __init ti_clk_init_features(void) 88 { 89 struct ti_clk_features features = { 0 }; 90 /* Fint setup for DPLLs */ 91 if (cpu_is_omap3430()) { 92 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; 93 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; 94 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; 95 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; 96 } else { 97 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; 98 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; 99 } 100 101 /* Bypass value setup for DPLLs */ 102 if (cpu_is_omap24xx()) { 103 features.dpll_bypass_vals |= 104 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | 105 (1 << OMAP2XXX_EN_DPLL_FRBYPASS); 106 } else if (cpu_is_omap34xx()) { 107 features.dpll_bypass_vals |= 108 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | 109 (1 << OMAP3XXX_EN_DPLL_FRBYPASS); 110 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || 111 soc_is_omap54xx() || soc_is_dra7xx()) { 112 features.dpll_bypass_vals |= 113 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | 114 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | 115 (1 << OMAP4XXX_EN_DPLL_MNBYPASS); 116 } 117 118 /* Jitter correction only available on OMAP343X */ 119 if (cpu_is_omap343x()) 120 features.flags |= TI_CLK_DPLL_HAS_FREQSEL; 121 122 /* Idlest value for interface clocks. 123 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 124 * 34xx reverses this, just to keep us on our toes 125 * AM35xx uses both, depending on the module. 126 */ 127 if (cpu_is_omap24xx()) 128 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; 129 else if (cpu_is_omap34xx()) 130 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; 131 132 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ 133 if (omap_rev() == OMAP3430_REV_ES1_0) 134 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; 135 136 /* Errata I810 for omap5 / dra7 */ 137 if (soc_is_omap54xx() || soc_is_dra7xx()) 138 features.flags |= TI_CLK_ERRATA_I810; 139 140 ti_clk_setup_features(&features); 141 } 142