1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/clk-private.h> 27 #include <asm/cpu.h> 28 29 #include <trace/events/power.h> 30 31 #include "soc.h" 32 #include "clockdomain.h" 33 #include "clock.h" 34 #include "cm.h" 35 #include "cm2xxx.h" 36 #include "cm3xxx.h" 37 #include "cm-regbits-24xx.h" 38 #include "cm-regbits-34xx.h" 39 #include "common.h" 40 41 /* 42 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 43 * for a module to indicate that it is no longer in idle 44 */ 45 #define MAX_MODULE_ENABLE_WAIT 100000 46 47 u16 cpu_mask; 48 49 /* 50 * Clock features setup. Used instead of CPU type checks. 51 */ 52 struct ti_clk_features ti_clk_features; 53 54 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 55 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 56 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 57 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 58 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 59 60 /* 61 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. 62 * From device data manual section 4.3 "DPLL and DLL Specifications". 63 */ 64 #define OMAP3PLUS_DPLL_FINT_MIN 32000 65 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 66 67 /* 68 * clkdm_control: if true, then when a clock is enabled in the 69 * hardware, its clockdomain will first be enabled; and when a clock 70 * is disabled in the hardware, its clockdomain will be disabled 71 * afterwards. 72 */ 73 static bool clkdm_control = true; 74 75 static LIST_HEAD(clk_hw_omap_clocks); 76 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 77 78 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 79 { 80 if (clk->flags & MEMMAP_ADDRESSING) { 81 struct clk_omap_reg *r = (struct clk_omap_reg *)® 82 writel_relaxed(val, clk_memmaps[r->index] + r->offset); 83 } else { 84 writel_relaxed(val, reg); 85 } 86 } 87 88 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 89 { 90 u32 val; 91 92 if (clk->flags & MEMMAP_ADDRESSING) { 93 struct clk_omap_reg *r = (struct clk_omap_reg *)® 94 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 95 } else { 96 val = readl_relaxed(reg); 97 } 98 99 return val; 100 } 101 102 /* 103 * Used for clocks that have the same value as the parent clock, 104 * divided by some factor 105 */ 106 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 107 unsigned long parent_rate) 108 { 109 struct clk_hw_omap *oclk; 110 111 if (!hw) { 112 pr_warn("%s: hw is NULL\n", __func__); 113 return -EINVAL; 114 } 115 116 oclk = to_clk_hw_omap(hw); 117 118 WARN_ON(!oclk->fixed_div); 119 120 return parent_rate / oclk->fixed_div; 121 } 122 123 /* 124 * OMAP2+ specific clock functions 125 */ 126 127 /* Private functions */ 128 129 130 /** 131 * _wait_idlest_generic - wait for a module to leave the idle state 132 * @clk: module clock to wait for (needed for register offsets) 133 * @reg: virtual address of module IDLEST register 134 * @mask: value to mask against to determine if the module is active 135 * @idlest: idle state indicator (0 or 1) for the clock 136 * @name: name of the clock (for printk) 137 * 138 * Wait for a module to leave idle, where its idle-status register is 139 * not inside the CM module. Returns 1 if the module left idle 140 * promptly, or 0 if the module did not leave idle before the timeout 141 * elapsed. XXX Deprecated - should be moved into drivers for the 142 * individual IP block that the IDLEST register exists in. 143 */ 144 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, 145 u32 mask, u8 idlest, const char *name) 146 { 147 int i = 0, ena = 0; 148 149 ena = (idlest) ? 0 : mask; 150 151 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), 152 MAX_MODULE_ENABLE_WAIT, i); 153 154 if (i < MAX_MODULE_ENABLE_WAIT) 155 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 156 name, i); 157 else 158 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 159 name, MAX_MODULE_ENABLE_WAIT); 160 161 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 162 }; 163 164 /** 165 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 166 * @clk: struct clk * belonging to the module 167 * 168 * If the necessary clocks for the OMAP hardware IP block that 169 * corresponds to clock @clk are enabled, then wait for the module to 170 * indicate readiness (i.e., to leave IDLE). This code does not 171 * belong in the clock code and will be moved in the medium term to 172 * module-dependent code. No return value. 173 */ 174 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 175 { 176 void __iomem *companion_reg, *idlest_reg; 177 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 178 s16 prcm_mod; 179 int r; 180 181 /* Not all modules have multiple clocks that their IDLEST depends on */ 182 if (clk->ops->find_companion) { 183 clk->ops->find_companion(clk, &companion_reg, &other_bit); 184 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) 185 return; 186 } 187 188 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 189 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 190 if (r) { 191 /* IDLEST register not in the CM module */ 192 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 193 idlest_val, __clk_get_name(clk->hw.clk)); 194 } else { 195 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 196 }; 197 } 198 199 /* Public functions */ 200 201 /** 202 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 203 * @clk: OMAP clock struct ptr to use 204 * 205 * Convert a clockdomain name stored in a struct clk 'clk' into a 206 * clockdomain pointer, and save it into the struct clk. Intended to be 207 * called during clk_register(). No return value. 208 */ 209 void omap2_init_clk_clkdm(struct clk_hw *hw) 210 { 211 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 212 struct clockdomain *clkdm; 213 const char *clk_name; 214 215 if (!clk->clkdm_name) 216 return; 217 218 clk_name = __clk_get_name(hw->clk); 219 220 clkdm = clkdm_lookup(clk->clkdm_name); 221 if (clkdm) { 222 pr_debug("clock: associated clk %s to clkdm %s\n", 223 clk_name, clk->clkdm_name); 224 clk->clkdm = clkdm; 225 } else { 226 pr_debug("clock: could not associate clk %s to clkdm %s\n", 227 clk_name, clk->clkdm_name); 228 } 229 } 230 231 /** 232 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 233 * 234 * Prevent the OMAP clock code from calling into the clockdomain code 235 * when a hardware clock in that clockdomain is enabled or disabled. 236 * Intended to be called at init time from omap*_clk_init(). No 237 * return value. 238 */ 239 void __init omap2_clk_disable_clkdm_control(void) 240 { 241 clkdm_control = false; 242 } 243 244 /** 245 * omap2_clk_dflt_find_companion - find companion clock to @clk 246 * @clk: struct clk * to find the companion clock of 247 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 248 * @other_bit: u8 ** to return the companion clock bit shift in 249 * 250 * Note: We don't need special code here for INVERT_ENABLE for the 251 * time being since INVERT_ENABLE only applies to clocks enabled by 252 * CM_CLKEN_PLL 253 * 254 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 255 * just a matter of XORing the bits. 256 * 257 * Some clocks don't have companion clocks. For example, modules with 258 * only an interface clock (such as MAILBOXES) don't have a companion 259 * clock. Right now, this code relies on the hardware exporting a bit 260 * in the correct companion register that indicates that the 261 * nonexistent 'companion clock' is active. Future patches will 262 * associate this type of code with per-module data structures to 263 * avoid this issue, and remove the casts. No return value. 264 */ 265 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 266 void __iomem **other_reg, u8 *other_bit) 267 { 268 u32 r; 269 270 /* 271 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 272 * it's just a matter of XORing the bits. 273 */ 274 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 275 276 *other_reg = (__force void __iomem *)r; 277 *other_bit = clk->enable_bit; 278 } 279 280 /** 281 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 282 * @clk: struct clk * to find IDLEST info for 283 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 284 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 285 * @idlest_val: u8 * to return the idle status indicator 286 * 287 * Return the CM_IDLEST register address and bit shift corresponding 288 * to the module that "owns" this clock. This default code assumes 289 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 290 * the IDLEST register address ID corresponds to the CM_*CLKEN 291 * register address ID (e.g., that CM_FCLKEN2 corresponds to 292 * CM_IDLEST2). This is not true for all modules. No return value. 293 */ 294 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 295 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 296 { 297 u32 r; 298 299 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 300 *idlest_reg = (__force void __iomem *)r; 301 *idlest_bit = clk->enable_bit; 302 303 /* 304 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 305 * 34xx reverses this, just to keep us on our toes 306 * AM35xx uses both, depending on the module. 307 */ 308 *idlest_val = ti_clk_features.cm_idlest_val; 309 } 310 311 /** 312 * omap2_dflt_clk_enable - enable a clock in the hardware 313 * @hw: struct clk_hw * of the clock to enable 314 * 315 * Enable the clock @hw in the hardware. We first call into the OMAP 316 * clockdomain code to "enable" the corresponding clockdomain if this 317 * is the first enabled user of the clockdomain. Then program the 318 * hardware to enable the clock. Then wait for the IP block that uses 319 * this clock to leave idle (if applicable). Returns the error value 320 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 321 * if @hw has a null clock enable_reg, or zero upon success. 322 */ 323 int omap2_dflt_clk_enable(struct clk_hw *hw) 324 { 325 struct clk_hw_omap *clk; 326 u32 v; 327 int ret = 0; 328 329 clk = to_clk_hw_omap(hw); 330 331 if (clkdm_control && clk->clkdm) { 332 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 333 if (ret) { 334 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", 335 __func__, __clk_get_name(hw->clk), 336 clk->clkdm->name, ret); 337 return ret; 338 } 339 } 340 341 if (unlikely(clk->enable_reg == NULL)) { 342 pr_err("%s: %s missing enable_reg\n", __func__, 343 __clk_get_name(hw->clk)); 344 ret = -EINVAL; 345 goto err; 346 } 347 348 /* FIXME should not have INVERT_ENABLE bit here */ 349 v = omap2_clk_readl(clk, clk->enable_reg); 350 if (clk->flags & INVERT_ENABLE) 351 v &= ~(1 << clk->enable_bit); 352 else 353 v |= (1 << clk->enable_bit); 354 omap2_clk_writel(v, clk, clk->enable_reg); 355 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ 356 357 if (clk->ops && clk->ops->find_idlest) 358 _omap2_module_wait_ready(clk); 359 360 return 0; 361 362 err: 363 if (clkdm_control && clk->clkdm) 364 clkdm_clk_disable(clk->clkdm, hw->clk); 365 return ret; 366 } 367 368 /** 369 * omap2_dflt_clk_disable - disable a clock in the hardware 370 * @hw: struct clk_hw * of the clock to disable 371 * 372 * Disable the clock @hw in the hardware, and call into the OMAP 373 * clockdomain code to "disable" the corresponding clockdomain if all 374 * clocks/hwmods in that clockdomain are now disabled. No return 375 * value. 376 */ 377 void omap2_dflt_clk_disable(struct clk_hw *hw) 378 { 379 struct clk_hw_omap *clk; 380 u32 v; 381 382 clk = to_clk_hw_omap(hw); 383 if (!clk->enable_reg) { 384 /* 385 * 'independent' here refers to a clock which is not 386 * controlled by its parent. 387 */ 388 pr_err("%s: independent clock %s has no enable_reg\n", 389 __func__, __clk_get_name(hw->clk)); 390 return; 391 } 392 393 v = omap2_clk_readl(clk, clk->enable_reg); 394 if (clk->flags & INVERT_ENABLE) 395 v |= (1 << clk->enable_bit); 396 else 397 v &= ~(1 << clk->enable_bit); 398 omap2_clk_writel(v, clk, clk->enable_reg); 399 /* No OCP barrier needed here since it is a disable operation */ 400 401 if (clkdm_control && clk->clkdm) 402 clkdm_clk_disable(clk->clkdm, hw->clk); 403 } 404 405 /** 406 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw 407 * @hw: struct clk_hw * of the clock being enabled 408 * 409 * Increment the usecount of the clockdomain of the clock pointed to 410 * by @hw; if the usecount is 1, the clockdomain will be "enabled." 411 * Only needed for clocks that don't use omap2_dflt_clk_enable() as 412 * their enable function pointer. Passes along the return value of 413 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a 414 * clockdomain, or 0 if clock framework-based clockdomain control is 415 * not implemented. 416 */ 417 int omap2_clkops_enable_clkdm(struct clk_hw *hw) 418 { 419 struct clk_hw_omap *clk; 420 int ret = 0; 421 422 clk = to_clk_hw_omap(hw); 423 424 if (unlikely(!clk->clkdm)) { 425 pr_err("%s: %s: no clkdm set ?!\n", __func__, 426 __clk_get_name(hw->clk)); 427 return -EINVAL; 428 } 429 430 if (unlikely(clk->enable_reg)) 431 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 432 __clk_get_name(hw->clk)); 433 434 if (!clkdm_control) { 435 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 436 __func__, __clk_get_name(hw->clk)); 437 return 0; 438 } 439 440 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 441 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 442 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); 443 444 return ret; 445 } 446 447 /** 448 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw 449 * @hw: struct clk_hw * of the clock being disabled 450 * 451 * Decrement the usecount of the clockdomain of the clock pointed to 452 * by @hw; if the usecount is 0, the clockdomain will be "disabled." 453 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their 454 * disable function pointer. No return value. 455 */ 456 void omap2_clkops_disable_clkdm(struct clk_hw *hw) 457 { 458 struct clk_hw_omap *clk; 459 460 clk = to_clk_hw_omap(hw); 461 462 if (unlikely(!clk->clkdm)) { 463 pr_err("%s: %s: no clkdm set ?!\n", __func__, 464 __clk_get_name(hw->clk)); 465 return; 466 } 467 468 if (unlikely(clk->enable_reg)) 469 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 470 __clk_get_name(hw->clk)); 471 472 if (!clkdm_control) { 473 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 474 __func__, __clk_get_name(hw->clk)); 475 return; 476 } 477 478 clkdm_clk_disable(clk->clkdm, hw->clk); 479 } 480 481 /** 482 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 483 * @hw: struct clk_hw * to check 484 * 485 * Return 1 if the clock represented by @hw is enabled in the 486 * hardware, or 0 otherwise. Intended for use in the struct 487 * clk_ops.is_enabled function pointer. 488 */ 489 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 490 { 491 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 492 u32 v; 493 494 v = omap2_clk_readl(clk, clk->enable_reg); 495 496 if (clk->flags & INVERT_ENABLE) 497 v ^= BIT(clk->enable_bit); 498 499 v &= BIT(clk->enable_bit); 500 501 return v ? 1 : 0; 502 } 503 504 static int __initdata mpurate; 505 506 /* 507 * By default we use the rate set by the bootloader. 508 * You can override this with mpurate= cmdline option. 509 */ 510 static int __init omap_clk_setup(char *str) 511 { 512 get_option(&str, &mpurate); 513 514 if (!mpurate) 515 return 1; 516 517 if (mpurate < 1000) 518 mpurate *= 1000000; 519 520 return 1; 521 } 522 __setup("mpurate=", omap_clk_setup); 523 524 /** 525 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock 526 * @clk: struct clk * to initialize 527 * 528 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used 529 * temporarily for autoidle handling, until this support can be 530 * integrated into the common clock framework code in some way. No 531 * return value. 532 */ 533 void omap2_init_clk_hw_omap_clocks(struct clk *clk) 534 { 535 struct clk_hw_omap *c; 536 537 if (__clk_get_flags(clk) & CLK_IS_BASIC) 538 return; 539 540 c = to_clk_hw_omap(__clk_get_hw(clk)); 541 list_add(&c->node, &clk_hw_omap_clocks); 542 } 543 544 /** 545 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that 546 * support it 547 * 548 * Enable clock autoidle on all OMAP clocks that have allow_idle 549 * function pointers associated with them. This function is intended 550 * to be temporary until support for this is added to the common clock 551 * code. Returns 0. 552 */ 553 int omap2_clk_enable_autoidle_all(void) 554 { 555 struct clk_hw_omap *c; 556 557 list_for_each_entry(c, &clk_hw_omap_clocks, node) 558 if (c->ops && c->ops->allow_idle) 559 c->ops->allow_idle(c); 560 561 of_ti_clk_allow_autoidle_all(); 562 563 return 0; 564 } 565 566 /** 567 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that 568 * support it 569 * 570 * Disable clock autoidle on all OMAP clocks that have allow_idle 571 * function pointers associated with them. This function is intended 572 * to be temporary until support for this is added to the common clock 573 * code. Returns 0. 574 */ 575 int omap2_clk_disable_autoidle_all(void) 576 { 577 struct clk_hw_omap *c; 578 579 list_for_each_entry(c, &clk_hw_omap_clocks, node) 580 if (c->ops && c->ops->deny_idle) 581 c->ops->deny_idle(c); 582 583 of_ti_clk_deny_autoidle_all(); 584 585 return 0; 586 } 587 588 /** 589 * omap2_clk_deny_idle - disable autoidle on an OMAP clock 590 * @clk: struct clk * to disable autoidle for 591 * 592 * Disable autoidle on an OMAP clock. 593 */ 594 int omap2_clk_deny_idle(struct clk *clk) 595 { 596 struct clk_hw_omap *c; 597 598 if (__clk_get_flags(clk) & CLK_IS_BASIC) 599 return -EINVAL; 600 601 c = to_clk_hw_omap(__clk_get_hw(clk)); 602 if (c->ops && c->ops->deny_idle) 603 c->ops->deny_idle(c); 604 return 0; 605 } 606 607 /** 608 * omap2_clk_allow_idle - enable autoidle on an OMAP clock 609 * @clk: struct clk * to enable autoidle for 610 * 611 * Enable autoidle on an OMAP clock. 612 */ 613 int omap2_clk_allow_idle(struct clk *clk) 614 { 615 struct clk_hw_omap *c; 616 617 if (__clk_get_flags(clk) & CLK_IS_BASIC) 618 return -EINVAL; 619 620 c = to_clk_hw_omap(__clk_get_hw(clk)); 621 if (c->ops && c->ops->allow_idle) 622 c->ops->allow_idle(c); 623 return 0; 624 } 625 626 /** 627 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 628 * @clk_names: ptr to an array of strings of clock names to enable 629 * @num_clocks: number of clock names in @clk_names 630 * 631 * Prepare and enable a list of clocks, named by @clk_names. No 632 * return value. XXX Deprecated; only needed until these clocks are 633 * properly claimed and enabled by the drivers or core code that uses 634 * them. XXX What code disables & calls clk_put on these clocks? 635 */ 636 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) 637 { 638 struct clk *init_clk; 639 int i; 640 641 for (i = 0; i < num_clocks; i++) { 642 init_clk = clk_get(NULL, clk_names[i]); 643 clk_prepare_enable(init_clk); 644 } 645 } 646 647 const struct clk_hw_omap_ops clkhwops_wait = { 648 .find_idlest = omap2_clk_dflt_find_idlest, 649 .find_companion = omap2_clk_dflt_find_companion, 650 }; 651 652 /** 653 * omap_clocks_register - register an array of omap_clk 654 * @ocs: pointer to an array of omap_clk to register 655 */ 656 void __init omap_clocks_register(struct omap_clk oclks[], int cnt) 657 { 658 struct omap_clk *c; 659 660 for (c = oclks; c < oclks + cnt; c++) { 661 clkdev_add(&c->lk); 662 if (!__clk_init(NULL, c->lk.clk)) 663 omap2_init_clk_hw_omap_clocks(c->lk.clk); 664 } 665 } 666 667 /** 668 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 669 * @mpurate_ck_name: clk name of the clock to change rate 670 * 671 * Change the ARM MPU clock rate to the rate specified on the command 672 * line, if one was specified. @mpurate_ck_name should be 673 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 674 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 675 * handled by the virt_prcm_set clock, but this should be handled by 676 * the OPP layer. XXX This is intended to be handled by the OPP layer 677 * code in the near future and should be removed from the clock code. 678 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 679 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 680 * cannot be found, or 0 upon success. 681 */ 682 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 683 { 684 struct clk *mpurate_ck; 685 int r; 686 687 if (!mpurate) 688 return -EINVAL; 689 690 mpurate_ck = clk_get(NULL, mpurate_ck_name); 691 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 692 return -ENOENT; 693 694 r = clk_set_rate(mpurate_ck, mpurate); 695 if (r < 0) { 696 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 697 mpurate_ck_name, mpurate, r); 698 clk_put(mpurate_ck); 699 return -EINVAL; 700 } 701 702 calibrate_delay(); 703 clk_put(mpurate_ck); 704 705 return 0; 706 } 707 708 /** 709 * omap2_clk_print_new_rates - print summary of current clock tree rates 710 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 711 * @core_ck_name: clk name for the on-chip CORE_CLK 712 * @mpu_ck_name: clk name for the ARM MPU clock 713 * 714 * Prints a short message to the console with the HFCLKIN oscillator 715 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 716 * Called by the boot-time MPU rate switching code. XXX This is intended 717 * to be handled by the OPP layer code in the near future and should be 718 * removed from the clock code. No return value. 719 */ 720 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 721 const char *core_ck_name, 722 const char *mpu_ck_name) 723 { 724 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 725 unsigned long hfclkin_rate; 726 727 mpu_ck = clk_get(NULL, mpu_ck_name); 728 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 729 return; 730 731 core_ck = clk_get(NULL, core_ck_name); 732 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 733 return; 734 735 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 736 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 737 return; 738 739 hfclkin_rate = clk_get_rate(hfclkin_ck); 740 741 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 742 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 743 (clk_get_rate(core_ck) / 1000000), 744 (clk_get_rate(mpu_ck) / 1000000)); 745 } 746 747 /** 748 * ti_clk_init_features - init clock features struct for the SoC 749 * 750 * Initializes the clock features struct based on the SoC type. 751 */ 752 void __init ti_clk_init_features(void) 753 { 754 /* Fint setup for DPLLs */ 755 if (cpu_is_omap3430()) { 756 ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; 757 ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; 758 ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; 759 ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; 760 } else { 761 ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; 762 ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; 763 } 764 765 /* Bypass value setup for DPLLs */ 766 if (cpu_is_omap24xx()) { 767 ti_clk_features.dpll_bypass_vals |= 768 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | 769 (1 << OMAP2XXX_EN_DPLL_FRBYPASS); 770 } else if (cpu_is_omap34xx()) { 771 ti_clk_features.dpll_bypass_vals |= 772 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | 773 (1 << OMAP3XXX_EN_DPLL_FRBYPASS); 774 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || 775 soc_is_omap54xx() || soc_is_dra7xx()) { 776 ti_clk_features.dpll_bypass_vals |= 777 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | 778 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | 779 (1 << OMAP4XXX_EN_DPLL_MNBYPASS); 780 } 781 782 /* Jitter correction only available on OMAP343X */ 783 if (cpu_is_omap343x()) 784 ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; 785 786 /* Idlest value for interface clocks. 787 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 788 * 34xx reverses this, just to keep us on our toes 789 * AM35xx uses both, depending on the module. 790 */ 791 if (cpu_is_omap24xx()) 792 ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; 793 else if (cpu_is_omap34xx()) 794 ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; 795 } 796