1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * DPLL + CORE_CLK composite clock functions
4  *
5  * Copyright (C) 2005-2008 Texas Instruments, Inc.
6  * Copyright (C) 2004-2010 Nokia Corporation
7  *
8  * Contacts:
9  * Richard Woodruff <r-woodruff2@ti.com>
10  * Paul Walmsley
11  *
12  * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
13  * Gordon McNutt and RidgeRun, Inc.
14  *
15  * XXX The DPLL and CORE clocks should be split into two separate clock
16  * types.
17  */
18 #undef DEBUG
19 
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/clk.h>
23 #include <linux/clk/ti.h>
24 #include <linux/io.h>
25 
26 #include "clock.h"
27 #include "clock2xxx.h"
28 #include "opp2xxx.h"
29 #include "cm2xxx.h"
30 #include "cm-regbits-24xx.h"
31 #include "sdrc.h"
32 #include "sram.h"
33 
34 /* #define DOWN_VARIABLE_DPLL 1 */		/* Experimental */
35 
36 /*
37  * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
38  * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
39  * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
40  */
41 static struct clk_hw_omap *dpll_core_ck;
42 
43 /**
44  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
45  *
46  * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
47  * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
48  * (the latter is unusual).  This currently should be called with
49  * struct clk *dpll_ck, which is a composite clock of dpll_ck and
50  * core_ck.
51  */
52 unsigned long omap2xxx_clk_get_core_rate(void)
53 {
54 	long long core_clk;
55 	u32 v;
56 
57 	WARN_ON(!dpll_core_ck);
58 
59 	core_clk = omap2_get_dpll_rate(dpll_core_ck);
60 
61 	v = omap2xxx_cm_get_core_clk_src();
62 
63 	if (v == CORE_CLK_SRC_32K)
64 		core_clk = 32768;
65 	else
66 		core_clk *= v;
67 
68 	return core_clk;
69 }
70 
71 /*
72  * Uses the current prcm set to tell if a rate is valid.
73  * You can go slower, but not faster within a given rate set.
74  */
75 static long omap2_dpllcore_round_rate(unsigned long target_rate)
76 {
77 	u32 high, low, core_clk_src;
78 
79 	core_clk_src = omap2xxx_cm_get_core_clk_src();
80 
81 	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
82 		high = curr_prcm_set->dpll_speed * 2;
83 		low = curr_prcm_set->dpll_speed;
84 	} else {				/* DPLL clockout x 2 */
85 		high = curr_prcm_set->dpll_speed;
86 		low = curr_prcm_set->dpll_speed / 2;
87 	}
88 
89 #ifdef DOWN_VARIABLE_DPLL
90 	if (target_rate > high)
91 		return high;
92 	else
93 		return target_rate;
94 #else
95 	if (target_rate > low)
96 		return high;
97 	else
98 		return low;
99 #endif
100 
101 }
102 
103 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
104 				    unsigned long parent_rate)
105 {
106 	return omap2xxx_clk_get_core_rate();
107 }
108 
109 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
110 			     unsigned long parent_rate)
111 {
112 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
113 	u32 cur_rate, low, mult, div, valid_rate, done_rate;
114 	u32 bypass = 0;
115 	struct prcm_config tmpset;
116 	const struct dpll_data *dd;
117 
118 	cur_rate = omap2xxx_clk_get_core_rate();
119 	mult = omap2xxx_cm_get_core_clk_src();
120 
121 	if ((rate == (cur_rate / 2)) && (mult == 2)) {
122 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
123 	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
124 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
125 	} else if (rate != cur_rate) {
126 		valid_rate = omap2_dpllcore_round_rate(rate);
127 		if (valid_rate != rate)
128 			return -EINVAL;
129 
130 		if (mult == 1)
131 			low = curr_prcm_set->dpll_speed;
132 		else
133 			low = curr_prcm_set->dpll_speed / 2;
134 
135 		dd = clk->dpll_data;
136 		if (!dd)
137 			return -EINVAL;
138 
139 		tmpset.cm_clksel1_pll =
140 			omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg);
141 		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
142 					   dd->div1_mask);
143 		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
144 		tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
145 		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
146 		if (rate > low) {
147 			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
148 			mult = ((rate / 2) / 1000000);
149 			done_rate = CORE_CLK_SRC_DPLL_X2;
150 		} else {
151 			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
152 			mult = (rate / 1000000);
153 			done_rate = CORE_CLK_SRC_DPLL;
154 		}
155 		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
156 		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
157 
158 		/* Worst case */
159 		tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
160 
161 		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */
162 			bypass = 1;
163 
164 		/* For omap2xxx_sdrc_init_params() */
165 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
166 
167 		/* Force dll lock mode */
168 		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
169 			       bypass);
170 
171 		/* Errata: ret dll entry state */
172 		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
173 		omap2xxx_sdrc_reprogram(done_rate, 0);
174 	}
175 
176 	return 0;
177 }
178 
179 /**
180  * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
181  * @clk: struct clk *dpll_ck
182  *
183  * Store a local copy of @clk in dpll_core_ck so other code can query
184  * the core rate without having to clk_get(), which can sleep.  Must
185  * only be called once.  No return value.  XXX If the clock
186  * registration process is ever changed such that dpll_ck is no longer
187  * statically defined, this code may need to change to increment some
188  * kind of use count on dpll_ck.
189  */
190 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
191 {
192 	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
193 	dpll_core_ck = to_clk_hw_omap(hw);
194 }
195