1# SPDX-License-Identifier: GPL-2.0-only 2menu "TI OMAP/AM/DM/DRA Family" 3 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 4 5config OMAP_HWMOD 6 bool 7 8config ARCH_OMAP2 9 bool "TI OMAP2" 10 depends on ARCH_MULTI_V6 11 select ARCH_OMAP2PLUS 12 select CPU_V6 13 select OMAP_HWMOD 14 select SOC_HAS_OMAP2_SDRC 15 16config ARCH_OMAP3 17 bool "TI OMAP3" 18 depends on ARCH_MULTI_V7 19 select ARCH_OMAP2PLUS 20 select ARM_CPU_SUSPEND 21 select OMAP_HWMOD 22 select OMAP_INTERCONNECT 23 select PM_OPP 24 select SOC_HAS_OMAP2_SDRC 25 select ARM_ERRATA_430973 26 27config ARCH_OMAP4 28 bool "TI OMAP4" 29 depends on ARCH_MULTI_V7 30 select ARCH_OMAP2PLUS 31 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 32 select ARM_CPU_SUSPEND 33 select ARM_ERRATA_720789 34 select ARM_GIC 35 select HAVE_ARM_SCU if SMP 36 select HAVE_ARM_TWD if SMP 37 select OMAP_INTERCONNECT 38 select OMAP_INTERCONNECT_BARRIER 39 select PL310_ERRATA_588369 if CACHE_L2X0 40 select PL310_ERRATA_727915 if CACHE_L2X0 41 select PM_OPP 42 select PM if CPU_IDLE 43 select ARM_ERRATA_754322 44 select ARM_ERRATA_775420 45 select OMAP_INTERCONNECT 46 47config SOC_OMAP5 48 bool "TI OMAP5" 49 depends on ARCH_MULTI_V7 50 select ARCH_OMAP2PLUS 51 select ARM_CPU_SUSPEND 52 select ARM_GIC 53 select HAVE_ARM_SCU if SMP 54 select HAVE_ARM_ARCH_TIMER 55 select ARM_ERRATA_798181 if SMP 56 select OMAP_INTERCONNECT 57 select OMAP_INTERCONNECT_BARRIER 58 select PM_OPP 59 select ZONE_DMA if ARM_LPAE 60 61config SOC_AM33XX 62 bool "TI AM33XX" 63 depends on ARCH_MULTI_V7 64 select ARCH_OMAP2PLUS 65 select ARM_CPU_SUSPEND 66 67config SOC_AM43XX 68 bool "TI AM43x" 69 depends on ARCH_MULTI_V7 70 select ARCH_OMAP2PLUS 71 select ARM_GIC 72 select MACH_OMAP_GENERIC 73 select HAVE_ARM_SCU 74 select GENERIC_CLOCKEVENTS_BROADCAST 75 select HAVE_ARM_TWD 76 select ARM_ERRATA_754322 77 select ARM_ERRATA_775420 78 select OMAP_INTERCONNECT 79 select ARM_CPU_SUSPEND 80 81config SOC_DRA7XX 82 bool "TI DRA7XX" 83 depends on ARCH_MULTI_V7 84 select ARCH_OMAP2PLUS 85 select ARM_CPU_SUSPEND 86 select ARM_GIC 87 select HAVE_ARM_SCU if SMP 88 select HAVE_ARM_ARCH_TIMER 89 select IRQ_CROSSBAR 90 select ARM_ERRATA_798181 if SMP 91 select OMAP_INTERCONNECT 92 select OMAP_INTERCONNECT_BARRIER 93 select PM_OPP 94 select ZONE_DMA if ARM_LPAE 95 select PINCTRL_TI_IODELAY if OF && PINCTRL 96 97config ARCH_OMAP2PLUS 98 bool 99 select ARCH_HAS_BANDGAP 100 select ARCH_HAS_RESET_CONTROLLER 101 select ARCH_OMAP 102 select CLKSRC_MMIO 103 select GENERIC_IRQ_CHIP 104 select GPIOLIB 105 select MACH_OMAP_GENERIC 106 select MEMORY 107 select MFD_SYSCON 108 select OMAP_DM_TIMER 109 select OMAP_GPMC 110 select PINCTRL 111 select PM 112 select PM_GENERIC_DOMAINS 113 select PM_GENERIC_DOMAINS_OF 114 select RESET_CONTROLLER 115 select SOC_BUS 116 select TI_SYSC 117 select OMAP_IRQCHIP 118 select CLKSRC_TI_32K 119 help 120 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 121 122config OMAP_INTERCONNECT_BARRIER 123 bool 124 select ARM_HEAVY_MB 125 126config ARCH_OMAP 127 bool 128 129if ARCH_OMAP2PLUS 130 131menu "TI OMAP2/3/4 Specific Features" 132 133config ARCH_OMAP2PLUS_TYPICAL 134 bool "Typical OMAP configuration" 135 default y 136 select AEABI 137 select HIGHMEM 138 select I2C 139 select I2C_OMAP 140 select MENELAUS if ARCH_OMAP2 141 select NEON if CPU_V7 142 select REGULATOR 143 select REGULATOR_FIXED_VOLTAGE 144 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 145 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 146 select VFP 147 help 148 Compile a kernel suitable for booting most boards 149 150config SOC_HAS_OMAP2_SDRC 151 bool "OMAP2 SDRAM Controller support" 152 153config SOC_HAS_REALTIME_COUNTER 154 bool "Real time free running counter" 155 depends on SOC_OMAP5 || SOC_DRA7XX 156 default y 157 158config POWER_AVS_OMAP 159 bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2" 160 depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM 161 select POWER_SUPPLY 162 help 163 Say Y to enable AVS(Adaptive Voltage Scaling) 164 support on OMAP containing the version 1 or 165 version 2 of the SmartReflex IP. 166 V1 is the 65nm version used in OMAP3430. 167 V2 is the update for the 45nm version of the IP used in OMAP3630 168 and OMAP4430 169 170 Please note, that by default SmartReflex is only 171 initialized and not enabled. To enable the automatic voltage 172 compensation for vdd mpu and vdd core from user space, 173 user must write 1 to 174 /debug/smartreflex/sr_<X>/autocomp, 175 where X is mpu_iva or core for OMAP3. 176 Optionally autocompensation can be enabled in the kernel 177 by default during system init via the enable_on_init flag 178 which an be passed as platform data to the smartreflex driver. 179 180config POWER_AVS_OMAP_CLASS3 181 bool "Class 3 mode of Smartreflex Implementation" 182 depends on POWER_AVS_OMAP && TWL4030_CORE 183 help 184 Say Y to enable Class 3 implementation of Smartreflex 185 186 Class 3 implementation of Smartreflex employs continuous hardware 187 voltage calibration. 188 189config OMAP3_L2_AUX_SECURE_SAVE_RESTORE 190 bool "OMAP3 HS/EMU save and restore for L2 AUX control register" 191 depends on ARCH_OMAP3 && PM 192 help 193 Without this option, L2 Auxiliary control register contents are 194 lost during off-mode entry on HS/EMU devices. This feature 195 requires support from PPA / boot-loader in HS/EMU devices, which 196 currently does not exist by default. 197 198config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 199 int "Service ID for the support routine to set L2 AUX control" 200 depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE 201 default 43 202 help 203 PPA routine service ID for setting L2 auxiliary control register. 204 205comment "OMAP Core Type" 206 depends on ARCH_OMAP2 207 208config SOC_OMAP2420 209 bool "OMAP2420 support" 210 depends on ARCH_OMAP2 211 default y 212 select OMAP_DM_TIMER 213 select SOC_HAS_OMAP2_SDRC 214 215config SOC_OMAP2430 216 bool "OMAP2430 support" 217 depends on ARCH_OMAP2 218 default y 219 select SOC_HAS_OMAP2_SDRC 220 221config SOC_OMAP3430 222 bool "OMAP3430 support" 223 depends on ARCH_OMAP3 224 default y 225 select SOC_HAS_OMAP2_SDRC 226 227config SOC_TI81XX 228 bool "TI81XX support" 229 depends on ARCH_OMAP3 230 default y 231 232comment "OMAP Legacy Platform Data Board Type" 233 depends on ARCH_OMAP2PLUS 234 235config MACH_OMAP_GENERIC 236 bool 237 238config MACH_OMAP2_TUSB6010 239 bool 240 depends on ARCH_OMAP2 && SOC_OMAP2420 241 default y if MACH_NOKIA_N8X0 242 243config MACH_NOKIA_N810 244 bool 245 246config MACH_NOKIA_N810_WIMAX 247 bool 248 249config MACH_NOKIA_N8X0 250 bool "Nokia N800/N810" 251 depends on SOC_OMAP2420 252 default y 253 select MACH_NOKIA_N810 254 select MACH_NOKIA_N810_WIMAX 255 256config OMAP3_SDRC_AC_TIMING 257 bool "Enable SDRC AC timing register changes" 258 depends on ARCH_OMAP3 259 help 260 If you know that none of your system initiators will attempt to 261 access SDRAM during CORE DVFS, select Y here. This should boost 262 SDRAM performance at lower CORE OPPs. There are relatively few 263 users who will wish to say yes at this point - almost everyone will 264 wish to say no. Selecting yes without understanding what is 265 going on could result in system crashes; 266 267endmenu 268 269endif 270 271config OMAP5_ERRATA_801819 272 bool "Errata 801819: An eviction from L1 data cache might stall indefinitely" 273 depends on SOC_OMAP5 || SOC_DRA7XX 274 help 275 A livelock can occur in the L2 cache arbitration that might prevent 276 a snoop from completing. Under certain conditions this can cause the 277 system to deadlock. 278 279endmenu 280