1 /* 2 * linux/arch/arm/mach-omap1/timer32k.c 3 * 4 * OMAP 32K Timer 5 * 6 * Copyright (C) 2004 - 2005 Nokia Corporation 7 * Partial timer rewrite and additional dynamic tick timer support by 8 * Tony Lindgen <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 10 * OMAP Dual-mode timer framework support by Timo Teras 11 * 12 * MPU timer code based on the older MPU timer code for OMAP 13 * Copyright (C) 2000 RidgeRun, Inc. 14 * Author: Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the 18 * Free Software Foundation; either version 2 of the License, or (at your 19 * option) any later version. 20 * 21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * You should have received a copy of the GNU General Public License along 33 * with this program; if not, write to the Free Software Foundation, Inc., 34 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/sched.h> 42 #include <linux/spinlock.h> 43 #include <linux/err.h> 44 #include <linux/clk.h> 45 #include <linux/clocksource.h> 46 #include <linux/clockchips.h> 47 #include <linux/io.h> 48 49 #include <asm/system.h> 50 #include <asm/leds.h> 51 #include <asm/irq.h> 52 #include <asm/mach/irq.h> 53 #include <asm/mach/time.h> 54 55 #include <plat/dmtimer.h> 56 57 #include <mach/hardware.h> 58 59 #include "common.h" 60 61 /* 62 * --------------------------------------------------------------------------- 63 * 32KHz OS timer 64 * 65 * This currently works only on 16xx, as 1510 does not have the continuous 66 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track 67 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer 68 * on 1510 would be possible, but the timer would not be as accurate as 69 * with the 32KHz synchronized timer. 70 * --------------------------------------------------------------------------- 71 */ 72 73 /* 16xx specific defines */ 74 #define OMAP1_32K_TIMER_BASE 0xfffb9000 75 #define OMAP1_32K_TIMER_CR 0x08 76 #define OMAP1_32K_TIMER_TVR 0x00 77 #define OMAP1_32K_TIMER_TCR 0x04 78 79 #define OMAP_32K_TICKS_PER_SEC (32768) 80 81 /* 82 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 83 * so with HZ = 128, TVR = 255. 84 */ 85 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1) 86 87 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 88 (((nr_jiffies) * (clock_rate)) / HZ) 89 90 static inline void omap_32k_timer_write(int val, int reg) 91 { 92 omap_writew(val, OMAP1_32K_TIMER_BASE + reg); 93 } 94 95 static inline unsigned long omap_32k_timer_read(int reg) 96 { 97 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff; 98 } 99 100 static inline void omap_32k_timer_start(unsigned long load_val) 101 { 102 if (!load_val) 103 load_val = 1; 104 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR); 105 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR); 106 } 107 108 static inline void omap_32k_timer_stop(void) 109 { 110 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR); 111 } 112 113 #define omap_32k_timer_ack_irq() 114 115 static int omap_32k_timer_set_next_event(unsigned long delta, 116 struct clock_event_device *dev) 117 { 118 omap_32k_timer_start(delta); 119 120 return 0; 121 } 122 123 static void omap_32k_timer_set_mode(enum clock_event_mode mode, 124 struct clock_event_device *evt) 125 { 126 omap_32k_timer_stop(); 127 128 switch (mode) { 129 case CLOCK_EVT_MODE_PERIODIC: 130 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 131 break; 132 case CLOCK_EVT_MODE_ONESHOT: 133 case CLOCK_EVT_MODE_UNUSED: 134 case CLOCK_EVT_MODE_SHUTDOWN: 135 break; 136 case CLOCK_EVT_MODE_RESUME: 137 break; 138 } 139 } 140 141 static struct clock_event_device clockevent_32k_timer = { 142 .name = "32k-timer", 143 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 144 .shift = 32, 145 .set_next_event = omap_32k_timer_set_next_event, 146 .set_mode = omap_32k_timer_set_mode, 147 }; 148 149 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) 150 { 151 struct clock_event_device *evt = &clockevent_32k_timer; 152 omap_32k_timer_ack_irq(); 153 154 evt->event_handler(evt); 155 156 return IRQ_HANDLED; 157 } 158 159 static struct irqaction omap_32k_timer_irq = { 160 .name = "32KHz timer", 161 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 162 .handler = omap_32k_timer_interrupt, 163 }; 164 165 static __init void omap_init_32k_timer(void) 166 { 167 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 168 169 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, 170 NSEC_PER_SEC, 171 clockevent_32k_timer.shift); 172 clockevent_32k_timer.max_delta_ns = 173 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer); 174 clockevent_32k_timer.min_delta_ns = 175 clockevent_delta2ns(1, &clockevent_32k_timer); 176 177 clockevent_32k_timer.cpumask = cpumask_of(0); 178 clockevents_register_device(&clockevent_32k_timer); 179 } 180 181 /* 182 * --------------------------------------------------------------------------- 183 * Timer initialization 184 * --------------------------------------------------------------------------- 185 */ 186 bool __init omap_32k_timer_init(void) 187 { 188 omap_init_clocksource_32k(); 189 omap_init_32k_timer(); 190 191 return true; 192 } 193