1 /* 2 * linux/arch/arm/mach-omap1/timer32k.c 3 * 4 * OMAP 32K Timer 5 * 6 * Copyright (C) 2004 - 2005 Nokia Corporation 7 * Partial timer rewrite and additional dynamic tick timer support by 8 * Tony Lindgen <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 10 * OMAP Dual-mode timer framework support by Timo Teras 11 * 12 * MPU timer code based on the older MPU timer code for OMAP 13 * Copyright (C) 2000 RidgeRun, Inc. 14 * Author: Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the 18 * Free Software Foundation; either version 2 of the License, or (at your 19 * option) any later version. 20 * 21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * You should have received a copy of the GNU General Public License along 33 * with this program; if not, write to the Free Software Foundation, Inc., 34 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/sched.h> 42 #include <linux/spinlock.h> 43 #include <linux/err.h> 44 #include <linux/clk.h> 45 #include <linux/clocksource.h> 46 #include <linux/clockchips.h> 47 48 #include <asm/system.h> 49 #include <asm/hardware.h> 50 #include <asm/io.h> 51 #include <asm/leds.h> 52 #include <asm/irq.h> 53 #include <asm/mach/irq.h> 54 #include <asm/mach/time.h> 55 #include <asm/arch/dmtimer.h> 56 57 struct sys_timer omap_timer; 58 59 /* 60 * --------------------------------------------------------------------------- 61 * 32KHz OS timer 62 * 63 * This currently works only on 16xx, as 1510 does not have the continuous 64 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track 65 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer 66 * on 1510 would be possible, but the timer would not be as accurate as 67 * with the 32KHz synchronized timer. 68 * --------------------------------------------------------------------------- 69 */ 70 71 #if defined(CONFIG_ARCH_OMAP16XX) 72 #define TIMER_32K_SYNCHRONIZED 0xfffbc410 73 #else 74 #error OMAP 32KHz timer does not currently work on 15XX! 75 #endif 76 77 /* 16xx specific defines */ 78 #define OMAP1_32K_TIMER_BASE 0xfffb9000 79 #define OMAP1_32K_TIMER_CR 0x08 80 #define OMAP1_32K_TIMER_TVR 0x00 81 #define OMAP1_32K_TIMER_TCR 0x04 82 83 #define OMAP_32K_TICKS_PER_SEC (32768) 84 85 /* 86 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 87 * so with HZ = 128, TVR = 255. 88 */ 89 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1) 90 91 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 92 (((nr_jiffies) * (clock_rate)) / HZ) 93 94 static inline void omap_32k_timer_write(int val, int reg) 95 { 96 omap_writew(val, OMAP1_32K_TIMER_BASE + reg); 97 } 98 99 static inline unsigned long omap_32k_timer_read(int reg) 100 { 101 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff; 102 } 103 104 static inline void omap_32k_timer_start(unsigned long load_val) 105 { 106 if (!load_val) 107 load_val = 1; 108 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR); 109 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR); 110 } 111 112 static inline void omap_32k_timer_stop(void) 113 { 114 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR); 115 } 116 117 #define omap_32k_timer_ack_irq() 118 119 static int omap_32k_timer_set_next_event(unsigned long delta, 120 struct clock_event_device *dev) 121 { 122 omap_32k_timer_start(delta); 123 124 return 0; 125 } 126 127 static void omap_32k_timer_set_mode(enum clock_event_mode mode, 128 struct clock_event_device *evt) 129 { 130 omap_32k_timer_stop(); 131 132 switch (mode) { 133 case CLOCK_EVT_MODE_PERIODIC: 134 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 135 break; 136 case CLOCK_EVT_MODE_ONESHOT: 137 case CLOCK_EVT_MODE_UNUSED: 138 case CLOCK_EVT_MODE_SHUTDOWN: 139 break; 140 case CLOCK_EVT_MODE_RESUME: 141 break; 142 } 143 } 144 145 static struct clock_event_device clockevent_32k_timer = { 146 .name = "32k-timer", 147 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 148 .shift = 32, 149 .set_next_event = omap_32k_timer_set_next_event, 150 .set_mode = omap_32k_timer_set_mode, 151 }; 152 153 /* 154 * The 32KHz synchronized timer is an additional timer on 16xx. 155 * It is always running. 156 */ 157 static inline unsigned long omap_32k_sync_timer_read(void) 158 { 159 return omap_readl(TIMER_32K_SYNCHRONIZED); 160 } 161 162 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) 163 { 164 struct clock_event_device *evt = &clockevent_32k_timer; 165 omap_32k_timer_ack_irq(); 166 167 evt->event_handler(evt); 168 169 return IRQ_HANDLED; 170 } 171 172 static struct irqaction omap_32k_timer_irq = { 173 .name = "32KHz timer", 174 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 175 .handler = omap_32k_timer_interrupt, 176 }; 177 178 static __init void omap_init_32k_timer(void) 179 { 180 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 181 182 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, 183 NSEC_PER_SEC, 184 clockevent_32k_timer.shift); 185 clockevent_32k_timer.max_delta_ns = 186 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer); 187 clockevent_32k_timer.min_delta_ns = 188 clockevent_delta2ns(1, &clockevent_32k_timer); 189 190 clockevent_32k_timer.cpumask = cpumask_of_cpu(0); 191 clockevents_register_device(&clockevent_32k_timer); 192 } 193 194 /* 195 * --------------------------------------------------------------------------- 196 * Timer initialization 197 * --------------------------------------------------------------------------- 198 */ 199 static void __init omap_timer_init(void) 200 { 201 #ifdef CONFIG_OMAP_DM_TIMER 202 omap_dm_timer_init(); 203 #endif 204 omap_init_32k_timer(); 205 } 206 207 struct sys_timer omap_timer = { 208 .init = omap_timer_init, 209 }; 210