1 /* 2 * linux/arch/arm/mach-omap1/time.c 3 * 4 * OMAP Timers 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Partial timer rewrite and additional dynamic tick timer support by 8 * Tony Lindgen <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 10 * 11 * MPU timer code based on the older MPU timer code for OMAP 12 * Copyright (C) 2000 RidgeRun, Inc. 13 * Author: Greg Lonnon <glonnon@ridgerun.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * You should have received a copy of the GNU General Public License along 32 * with this program; if not, write to the Free Software Foundation, Inc., 33 * 675 Mass Ave, Cambridge, MA 02139, USA. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/sched.h> 41 #include <linux/spinlock.h> 42 #include <linux/clk.h> 43 #include <linux/err.h> 44 #include <linux/clocksource.h> 45 #include <linux/clockchips.h> 46 #include <linux/io.h> 47 48 #include <asm/system.h> 49 #include <mach/hardware.h> 50 #include <asm/leds.h> 51 #include <asm/irq.h> 52 #include <asm/sched_clock.h> 53 54 #include <asm/mach/irq.h> 55 #include <asm/mach/time.h> 56 57 #include <plat/common.h> 58 59 #ifdef CONFIG_OMAP_MPU_TIMER 60 61 #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE 62 #define OMAP_MPU_TIMER_OFFSET 0x100 63 64 typedef struct { 65 u32 cntl; /* CNTL_TIMER, R/W */ 66 u32 load_tim; /* LOAD_TIM, W */ 67 u32 read_tim; /* READ_TIM, R */ 68 } omap_mpu_timer_regs_t; 69 70 #define omap_mpu_timer_base(n) \ 71 ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ 72 (n)*OMAP_MPU_TIMER_OFFSET)) 73 74 static inline unsigned long notrace omap_mpu_timer_read(int nr) 75 { 76 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); 77 return readl(&timer->read_tim); 78 } 79 80 static inline void omap_mpu_set_autoreset(int nr) 81 { 82 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); 83 84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); 85 } 86 87 static inline void omap_mpu_remove_autoreset(int nr) 88 { 89 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); 90 91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); 92 } 93 94 static inline void omap_mpu_timer_start(int nr, unsigned long load_val, 95 int autoreset) 96 { 97 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); 98 unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST; 99 100 if (autoreset) 101 timerflags |= MPU_TIMER_AR; 102 103 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); 104 udelay(1); 105 writel(load_val, &timer->load_tim); 106 udelay(1); 107 writel(timerflags, &timer->cntl); 108 } 109 110 static inline void omap_mpu_timer_stop(int nr) 111 { 112 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); 113 114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); 115 } 116 117 /* 118 * --------------------------------------------------------------------------- 119 * MPU timer 1 ... count down to zero, interrupt, reload 120 * --------------------------------------------------------------------------- 121 */ 122 static int omap_mpu_set_next_event(unsigned long cycles, 123 struct clock_event_device *evt) 124 { 125 omap_mpu_timer_start(0, cycles, 0); 126 return 0; 127 } 128 129 static void omap_mpu_set_mode(enum clock_event_mode mode, 130 struct clock_event_device *evt) 131 { 132 switch (mode) { 133 case CLOCK_EVT_MODE_PERIODIC: 134 omap_mpu_set_autoreset(0); 135 break; 136 case CLOCK_EVT_MODE_ONESHOT: 137 omap_mpu_timer_stop(0); 138 omap_mpu_remove_autoreset(0); 139 break; 140 case CLOCK_EVT_MODE_UNUSED: 141 case CLOCK_EVT_MODE_SHUTDOWN: 142 case CLOCK_EVT_MODE_RESUME: 143 break; 144 } 145 } 146 147 static struct clock_event_device clockevent_mpu_timer1 = { 148 .name = "mpu_timer1", 149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 150 .shift = 32, 151 .set_next_event = omap_mpu_set_next_event, 152 .set_mode = omap_mpu_set_mode, 153 }; 154 155 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id) 156 { 157 struct clock_event_device *evt = &clockevent_mpu_timer1; 158 159 evt->event_handler(evt); 160 161 return IRQ_HANDLED; 162 } 163 164 static struct irqaction omap_mpu_timer1_irq = { 165 .name = "mpu_timer1", 166 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 167 .handler = omap_mpu_timer1_interrupt, 168 }; 169 170 static __init void omap_init_mpu_timer(unsigned long rate) 171 { 172 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); 173 omap_mpu_timer_start(0, (rate / HZ) - 1, 1); 174 175 clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC, 176 clockevent_mpu_timer1.shift); 177 clockevent_mpu_timer1.max_delta_ns = 178 clockevent_delta2ns(-1, &clockevent_mpu_timer1); 179 clockevent_mpu_timer1.min_delta_ns = 180 clockevent_delta2ns(1, &clockevent_mpu_timer1); 181 182 clockevent_mpu_timer1.cpumask = cpumask_of(0); 183 clockevents_register_device(&clockevent_mpu_timer1); 184 } 185 186 187 /* 188 * --------------------------------------------------------------------------- 189 * MPU timer 2 ... free running 32-bit clock source and scheduler clock 190 * --------------------------------------------------------------------------- 191 */ 192 193 static DEFINE_CLOCK_DATA(cd); 194 195 static inline unsigned long long notrace _omap_mpu_sched_clock(void) 196 { 197 u32 cyc = ~omap_mpu_timer_read(1); 198 return cyc_to_sched_clock(&cd, cyc, (u32)~0); 199 } 200 201 #ifndef CONFIG_OMAP_32K_TIMER 202 unsigned long long notrace sched_clock(void) 203 { 204 return _omap_mpu_sched_clock(); 205 } 206 #else 207 static unsigned long long notrace omap_mpu_sched_clock(void) 208 { 209 return _omap_mpu_sched_clock(); 210 } 211 #endif 212 213 static void notrace mpu_update_sched_clock(void) 214 { 215 u32 cyc = ~omap_mpu_timer_read(1); 216 update_sched_clock(&cd, cyc, (u32)~0); 217 } 218 219 static void __init omap_init_clocksource(unsigned long rate) 220 { 221 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1); 222 static char err[] __initdata = KERN_ERR 223 "%s: can't register clocksource!\n"; 224 225 omap_mpu_timer_start(1, ~0, 1); 226 init_sched_clock(&cd, mpu_update_sched_clock, 32, rate); 227 228 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, 229 300, 32, clocksource_mmio_readl_down)) 230 printk(err, "mpu_timer2"); 231 } 232 233 static void __init omap_mpu_timer_init(void) 234 { 235 struct clk *ck_ref = clk_get(NULL, "ck_ref"); 236 unsigned long rate; 237 238 BUG_ON(IS_ERR(ck_ref)); 239 240 rate = clk_get_rate(ck_ref); 241 clk_put(ck_ref); 242 243 /* PTV = 0 */ 244 rate /= 2; 245 246 omap_init_mpu_timer(rate); 247 omap_init_clocksource(rate); 248 } 249 250 #else 251 static inline void omap_mpu_timer_init(void) 252 { 253 pr_err("Bogus timer, should not happen\n"); 254 } 255 #endif /* CONFIG_OMAP_MPU_TIMER */ 256 257 #if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER) 258 static unsigned long long (*preferred_sched_clock)(void); 259 260 unsigned long long notrace sched_clock(void) 261 { 262 if (!preferred_sched_clock) 263 return 0; 264 265 return preferred_sched_clock(); 266 } 267 268 static inline void preferred_sched_clock_init(bool use_32k_sched_clock) 269 { 270 if (use_32k_sched_clock) 271 preferred_sched_clock = omap_32k_sched_clock; 272 else 273 preferred_sched_clock = omap_mpu_sched_clock; 274 } 275 #else 276 static inline void preferred_sched_clock_init(bool use_32k_sched_clcok) 277 { 278 } 279 #endif 280 281 static inline int omap_32k_timer_usable(void) 282 { 283 int res = false; 284 285 if (cpu_is_omap730() || cpu_is_omap15xx()) 286 return res; 287 288 #ifdef CONFIG_OMAP_32K_TIMER 289 res = omap_32k_timer_init(); 290 #endif 291 292 return res; 293 } 294 295 /* 296 * --------------------------------------------------------------------------- 297 * Timer initialization 298 * --------------------------------------------------------------------------- 299 */ 300 static void __init omap1_timer_init(void) 301 { 302 if (omap_32k_timer_usable()) { 303 preferred_sched_clock_init(1); 304 } else { 305 omap_mpu_timer_init(); 306 preferred_sched_clock_init(0); 307 } 308 } 309 310 struct sys_timer omap1_timer = { 311 .init = omap1_timer_init, 312 }; 313