xref: /openbmc/linux/arch/arm/mach-omap1/sleep.S (revision fea88a0c) 
1/*
2 * linux/arch/arm/mach-omap1/sleep.S
3 *
4 * Low-level OMAP7XX/1510/1610 sleep/wakeUp support
5 *
6 * Initial SA1110 code:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Adapted for PXA by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Support for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 */
34
35#include <linux/linkage.h>
36
37#include <asm/assembler.h>
38
39#include "iomap.h"
40#include "pm.h"
41
42		.text
43
44
45/*
46 * Forces OMAP into deep sleep state
47 *
48 * omapXXXX_cpu_suspend()
49 *
50 * The values of the registers ARM_IDLECT1 and ARM_IDLECT2 are passed
51 * as arg0 and arg1 from caller. arg0 is stored in register r0 and arg1
52 * in register r1.
53 *
54 * Note: This code get's copied to internal SRAM at boot. When the OMAP
55 *	 wakes up it continues execution at the point it went to sleep.
56 *
57 * Note: Because of errata work arounds we have processor specific functions
58 *       here. They are mostly the same, but slightly different.
59 *
60 */
61
62#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
63	.align	3
64ENTRY(omap7xx_cpu_suspend)
65
66	@ save registers on stack
67	stmfd	sp!, {r0 - r12, lr}
68
69	@ Drain write cache
70	mov	r4, #0
71	mcr	p15, 0, r0, c7, c10, 4
72	nop
73
74	@ load base address of Traffic Controller
75	mov	r6, #TCMIF_ASM_BASE & 0xff000000
76	orr	r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
77	orr	r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
78
79	@ prepare to put SDRAM into self-refresh manually
80	ldr	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
81	orr	r9, r7, #SELF_REFRESH_MODE & 0xff000000
82	orr	r9, r9, #SELF_REFRESH_MODE & 0x000000ff
83	str	r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
84
85	@ prepare to put EMIFS to Sleep
86	ldr	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87	orr	r9, r8, #IDLE_EMIFS_REQUEST & 0xff
88	str	r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
89
90	@ load base address of ARM_IDLECT1 and ARM_IDLECT2
91	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
92	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
93	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
94
95	@ turn off clock domains
96	@ do not disable PERCK (0x04)
97	mov	r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
98	orr	r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
99	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
100
101	@ request ARM idle
102	mov	r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
103	orr	r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
104	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
105
106	@ disable instruction cache
107	mrc	p15, 0, r9, c1, c0, 0
108	bic	r2, r9, #0x1000
109	mcr	p15, 0, r2, c1, c0, 0
110	nop
111
112/*
113 * Let's wait for the next wake up event to wake us up. r0 can't be
114 * used here because r0 holds ARM_IDLECT1
115 */
116	mov	r2, #0
117	mcr	p15, 0, r2, c7, c0, 4		@ wait for interrupt
118/*
119 * omap7xx_cpu_suspend()'s resume point.
120 *
121 * It will just start executing here, so we'll restore stuff from the
122 * stack.
123 */
124	@ re-enable Icache
125	mcr	p15, 0, r9, c1, c0, 0
126
127	@ reset the ARM_IDLECT1 and ARM_IDLECT2.
128	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
129	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
130
131	@ Restore EMIFF controls
132	str	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
133	str	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
134
135	@ restore regs and return
136	ldmfd	sp!, {r0 - r12, pc}
137
138ENTRY(omap7xx_cpu_suspend_sz)
139	.word	. - omap7xx_cpu_suspend
140#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
141
142#ifdef CONFIG_ARCH_OMAP15XX
143	.align	3
144ENTRY(omap1510_cpu_suspend)
145
146	@ save registers on stack
147	stmfd	sp!, {r0 - r12, lr}
148
149	@ load base address of Traffic Controller
150	mov	r4, #TCMIF_ASM_BASE & 0xff000000
151	orr	r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
152	orr	r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
153
154	@ work around errata of OMAP1510 PDE bit for TC shut down
155	@ clear PDE bit
156	ldr	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
157	bic	r5, r5, #PDE_BIT & 0xff
158	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
159
160	@ set PWD_EN bit
161	and	r5, r5, #PWD_EN_BIT & 0xff
162	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
163
164	@ prepare to put SDRAM into self-refresh manually
165	ldr	r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
166	orr	r5, r5, #SELF_REFRESH_MODE & 0xff000000
167	orr	r5, r5, #SELF_REFRESH_MODE & 0x000000ff
168	str	r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
169
170	@ prepare to put EMIFS to Sleep
171	ldr	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
172	orr	r5, r5, #IDLE_EMIFS_REQUEST & 0xff
173	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
174
175	@ load base address of ARM_IDLECT1 and ARM_IDLECT2
176	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
177	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
178	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
179
180	@ turn off clock domains
181	mov	r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
182	orr	r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
183	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
184
185	@ request ARM idle
186	mov	r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
187	orr	r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
188	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
189
190	mov	r5, #IDLE_WAIT_CYCLES & 0xff
191	orr	r5, r5, #IDLE_WAIT_CYCLES & 0xff00
192l_1510_2:
193	subs	r5, r5, #1
194	bne	l_1510_2
195/*
196 * Let's wait for the next wake up event to wake us up. r0 can't be
197 * used here because r0 holds ARM_IDLECT1
198 */
199	mov	r2, #0
200	mcr	p15, 0, r2, c7, c0, 4		@ wait for interrupt
201/*
202 * omap1510_cpu_suspend()'s resume point.
203 *
204 * It will just start executing here, so we'll restore stuff from the
205 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
206 */
207	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
208	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
209
210	@ restore regs and return
211	ldmfd	sp!, {r0 - r12, pc}
212
213ENTRY(omap1510_cpu_suspend_sz)
214	.word	. - omap1510_cpu_suspend
215#endif /* CONFIG_ARCH_OMAP15XX */
216
217#if defined(CONFIG_ARCH_OMAP16XX)
218	.align	3
219ENTRY(omap1610_cpu_suspend)
220
221	@ save registers on stack
222	stmfd	sp!, {r0 - r12, lr}
223
224	@ Drain write cache
225	mov	r4, #0
226	mcr	p15, 0, r0, c7, c10, 4
227	nop
228
229	@ Load base address of Traffic Controller
230	mov	r6, #TCMIF_ASM_BASE & 0xff000000
231	orr	r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
232	orr	r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
233
234	@ Prepare to put SDRAM into self-refresh manually
235	ldr	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
236	orr	r9, r7, #SELF_REFRESH_MODE & 0xff000000
237	orr	r9, r9, #SELF_REFRESH_MODE & 0x000000ff
238	str	r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
239
240	@ Prepare to put EMIFS to Sleep
241	ldr	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
242	orr	r9, r8, #IDLE_EMIFS_REQUEST & 0xff
243	str	r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
244
245	@ Load base address of ARM_IDLECT1 and ARM_IDLECT2
246	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
247	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
248	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
249
250	@ Turn off clock domains
251	@ Do not disable PERCK (0x04)
252	mov	r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
253	orr	r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
254	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
255
256	@ Request ARM idle
257	mov	r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
258	orr	r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
259	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
260
261/*
262 * Let's wait for the next wake up event to wake us up. r0 can't be
263 * used here because r0 holds ARM_IDLECT1
264 */
265	mov	r2, #0
266	mcr	p15, 0, r2, c7, c0, 4		@ wait for interrupt
267
268	@ Errata (HEL3SU467, section 1.4.4) specifies nop-instructions
269	@ according to this formula:
270	@ 2 + (4*DPLL_MULT)/DPLL_DIV/ARMDIV
271	@ Max DPLL_MULT = 18
272	@ DPLL_DIV = 1
273	@ ARMDIV = 1
274	@ => 74 nop-instructions
275	nop
276	nop
277	nop
278	nop
279	nop
280	nop
281	nop
282	nop
283	nop
284	nop	@10
285	nop
286	nop
287	nop
288	nop
289	nop
290	nop
291	nop
292	nop
293	nop
294	nop	@20
295	nop
296	nop
297	nop
298	nop
299	nop
300	nop
301	nop
302	nop
303	nop
304	nop	@30
305	nop
306	nop
307	nop
308	nop
309	nop
310	nop
311	nop
312	nop
313	nop
314	nop	@40
315	nop
316	nop
317	nop
318	nop
319	nop
320	nop
321	nop
322	nop
323	nop
324	nop	@50
325	nop
326	nop
327	nop
328	nop
329	nop
330	nop
331	nop
332	nop
333	nop
334	nop	@60
335	nop
336	nop
337	nop
338	nop
339	nop
340	nop
341	nop
342	nop
343	nop
344	nop	@70
345	nop
346	nop
347	nop
348	nop	@74
349/*
350 * omap1610_cpu_suspend()'s resume point.
351 *
352 * It will just start executing here, so we'll restore stuff from the
353 * stack.
354 */
355	@ Restore the ARM_IDLECT1 and ARM_IDLECT2.
356	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
357	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
358
359	@ Restore EMIFF controls
360	str	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
361	str	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
362
363	@ Restore regs and return
364	ldmfd	sp!, {r0 - r12, pc}
365
366ENTRY(omap1610_cpu_suspend_sz)
367	.word	. - omap1610_cpu_suspend
368#endif /* CONFIG_ARCH_OMAP16XX */
369