1 /* 2 * arch/arm/mach-omap1/pm.h 3 * 4 * Header file for OMAP1 Power Management Routines 5 * 6 * Author: MontaVista Software, Inc. 7 * support@mvista.com 8 * 9 * Copyright 2002 MontaVista Software Inc. 10 * 11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 */ 33 34 #ifndef __ARCH_ARM_MACH_OMAP1_PM_H 35 #define __ARCH_ARM_MACH_OMAP1_PM_H 36 37 /* 38 * ---------------------------------------------------------------------------- 39 * Register and offset definitions to be used in PM assembler code 40 * ---------------------------------------------------------------------------- 41 */ 42 #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00) 43 #define ARM_IDLECT1_ASM_OFFSET 0x04 44 #define ARM_IDLECT2_ASM_OFFSET 0x08 45 46 #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00) 47 #define EMIFS_CONFIG_ASM_OFFSET 0x0c 48 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 49 50 /* 51 * ---------------------------------------------------------------------------- 52 * Power management bitmasks 53 * ---------------------------------------------------------------------------- 54 */ 55 #define IDLE_WAIT_CYCLES 0x00000fff 56 #define PERIPHERAL_ENABLE 0x2 57 58 #define SELF_REFRESH_MODE 0x0c000001 59 #define IDLE_EMIFS_REQUEST 0xc 60 #define MODEM_32K_EN 0x1 61 #define PER_EN 0x1 62 63 #define CPU_SUSPEND_SIZE 200 64 #define ULPD_LOW_PWR_EN 0x0001 65 #define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010 66 #define ULPD_SETUP_ANALOG_CELL_3_VAL 0 67 #define ULPD_POWER_CTRL_REG_VAL 0x0219 68 69 #define DSP_IDLE_DELAY 10 70 #define DSP_IDLE 0x0040 71 #define DSP_RST 0x0004 72 #define DSP_ENABLE 0x0002 73 #define SUFFICIENT_DSP_RESET_TIME 1000 74 #define DEFAULT_MPUI_CONFIG 0x05cf 75 #define ENABLE_XORCLK 0x2 76 #define DSP_CLOCK_ENABLE 0x2000 77 #define DSP_IDLE_MODE 0x2 78 #define TC_IDLE_REQUEST (0x0000000c) 79 80 #define IRQ_LEVEL2 (1<<0) 81 #define IRQ_KEYBOARD (1<<1) 82 #define IRQ_UART2 (1<<15) 83 84 #define PDE_BIT 0x08 85 #define PWD_EN_BIT 0x04 86 #define EN_PERCK_BIT 0x04 87 88 #define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7 89 #define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5 90 #define OMAP1510_IDLE_LOOP_REQUEST 0x0c00 91 #define OMAP1510_IDLE_CLOCK_DOMAINS 0x2 92 93 /* Both big sleep and deep sleep use same values. Difference is in ULPD. */ 94 #define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7 95 #define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7 96 #define OMAP1610_IDLECT3_VAL 0x3f 97 #define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c 98 #define OMAP1610_IDLECT3 0xfffece24 99 #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 100 101 #define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 102 #define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 103 #define OMAP730_IDLECT3_VAL 0x3f 104 #define OMAP730_IDLECT3 0xfffece24 105 #define OMAP730_IDLE_LOOP_REQUEST 0x0C00 106 107 #if !defined(CONFIG_ARCH_OMAP730) && \ 108 !defined(CONFIG_ARCH_OMAP15XX) && \ 109 !defined(CONFIG_ARCH_OMAP16XX) 110 #warning "Power management for this processor not implemented yet" 111 #endif 112 113 #ifndef __ASSEMBLER__ 114 115 #include <linux/clk.h> 116 117 extern struct kset power_subsys; 118 119 extern void prevent_idle_sleep(void); 120 extern void allow_idle_sleep(void); 121 122 extern void omap1_pm_idle(void); 123 extern void omap1_pm_suspend(void); 124 125 extern void omap730_cpu_suspend(unsigned short, unsigned short); 126 extern void omap1510_cpu_suspend(unsigned short, unsigned short); 127 extern void omap1610_cpu_suspend(unsigned short, unsigned short); 128 extern void omap730_idle_loop_suspend(void); 129 extern void omap1510_idle_loop_suspend(void); 130 extern void omap1610_idle_loop_suspend(void); 131 132 extern unsigned int omap730_cpu_suspend_sz; 133 extern unsigned int omap1510_cpu_suspend_sz; 134 extern unsigned int omap1610_cpu_suspend_sz; 135 extern unsigned int omap730_idle_loop_suspend_sz; 136 extern unsigned int omap1510_idle_loop_suspend_sz; 137 extern unsigned int omap1610_idle_loop_suspend_sz; 138 139 #ifdef CONFIG_OMAP_SERIAL_WAKE 140 extern void omap_serial_wake_trigger(int enable); 141 #else 142 #define omap_serial_wakeup_init() {} 143 #define omap_serial_wake_trigger(x) {} 144 #endif /* CONFIG_OMAP_SERIAL_WAKE */ 145 146 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) 147 #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) 148 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] 149 150 #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) 151 #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) 152 #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] 153 154 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) 155 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) 156 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] 157 158 #define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) 159 #define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) 160 #define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] 161 162 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) 163 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) 164 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] 165 166 #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x) 167 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) 168 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] 169 170 /* 171 * List of global OMAP registers to preserve. 172 * More ones like CP and general purpose register values are preserved 173 * with the stack pointer in sleep.S. 174 */ 175 176 enum arm_save_state { 177 ARM_SLEEP_SAVE_START = 0, 178 /* 179 * MPU control registers 32 bits 180 */ 181 ARM_SLEEP_SAVE_ARM_CKCTL, 182 ARM_SLEEP_SAVE_ARM_IDLECT1, 183 ARM_SLEEP_SAVE_ARM_IDLECT2, 184 ARM_SLEEP_SAVE_ARM_IDLECT3, 185 ARM_SLEEP_SAVE_ARM_EWUPCT, 186 ARM_SLEEP_SAVE_ARM_RSTCT1, 187 ARM_SLEEP_SAVE_ARM_RSTCT2, 188 ARM_SLEEP_SAVE_ARM_SYSST, 189 ARM_SLEEP_SAVE_SIZE 190 }; 191 192 enum dsp_save_state { 193 DSP_SLEEP_SAVE_START = 0, 194 /* 195 * DSP registers 16 bits 196 */ 197 DSP_SLEEP_SAVE_DSP_IDLECT2, 198 DSP_SLEEP_SAVE_SIZE 199 }; 200 201 enum ulpd_save_state { 202 ULPD_SLEEP_SAVE_START = 0, 203 /* 204 * ULPD registers 16 bits 205 */ 206 ULPD_SLEEP_SAVE_ULPD_IT_STATUS, 207 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL, 208 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ, 209 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ, 210 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL, 211 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL, 212 ULPD_SLEEP_SAVE_SIZE 213 }; 214 215 enum mpui1510_save_state { 216 MPUI1510_SLEEP_SAVE_START = 0, 217 /* 218 * MPUI registers 32 bits 219 */ 220 MPUI1510_SLEEP_SAVE_MPUI_CTRL, 221 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 222 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 223 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS, 224 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 225 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, 226 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, 227 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, 228 #if defined(CONFIG_ARCH_OMAP15XX) 229 MPUI1510_SLEEP_SAVE_SIZE 230 #else 231 MPUI1510_SLEEP_SAVE_SIZE = 0 232 #endif 233 }; 234 235 enum mpui730_save_state { 236 MPUI730_SLEEP_SAVE_START = 0, 237 /* 238 * MPUI registers 32 bits 239 */ 240 MPUI730_SLEEP_SAVE_MPUI_CTRL, 241 MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 242 MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 243 MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, 244 MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 245 MPUI730_SLEEP_SAVE_EMIFS_CONFIG, 246 MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, 247 MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, 248 MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, 249 #if defined(CONFIG_ARCH_OMAP730) 250 MPUI730_SLEEP_SAVE_SIZE 251 #else 252 MPUI730_SLEEP_SAVE_SIZE = 0 253 #endif 254 }; 255 256 enum mpui1610_save_state { 257 MPUI1610_SLEEP_SAVE_START = 0, 258 /* 259 * MPUI registers 32 bits 260 */ 261 MPUI1610_SLEEP_SAVE_MPUI_CTRL, 262 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 263 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 264 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS, 265 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 266 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG, 267 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR, 268 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR, 269 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR, 270 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR, 271 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR, 272 #if defined(CONFIG_ARCH_OMAP16XX) 273 MPUI1610_SLEEP_SAVE_SIZE 274 #else 275 MPUI1610_SLEEP_SAVE_SIZE = 0 276 #endif 277 }; 278 279 #endif /* ASSEMBLER */ 280 #endif /* __ASM_ARCH_OMAP_PM_H */ 281