1 /* 2 * arch/arm/mach-omap1/pm.h 3 * 4 * Header file for OMAP1 Power Management Routines 5 * 6 * Author: MontaVista Software, Inc. 7 * support@mvista.com 8 * 9 * Copyright 2002 MontaVista Software Inc. 10 * 11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 */ 33 34 #ifndef __ARCH_ARM_MACH_OMAP1_PM_H 35 #define __ARCH_ARM_MACH_OMAP1_PM_H 36 37 #include <linux/soc/ti/omap1-io.h> 38 39 /* 40 * ---------------------------------------------------------------------------- 41 * Register and offset definitions to be used in PM assembler code 42 * ---------------------------------------------------------------------------- 43 */ 44 #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00) 45 #define ARM_IDLECT1_ASM_OFFSET 0x04 46 #define ARM_IDLECT2_ASM_OFFSET 0x08 47 48 #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00) 49 #define EMIFS_CONFIG_ASM_OFFSET 0x0c 50 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 51 52 /* 53 * ---------------------------------------------------------------------------- 54 * Power management bitmasks 55 * ---------------------------------------------------------------------------- 56 */ 57 #define IDLE_WAIT_CYCLES 0x00000fff 58 #define PERIPHERAL_ENABLE 0x2 59 60 #define SELF_REFRESH_MODE 0x0c000001 61 #define IDLE_EMIFS_REQUEST 0xc 62 #define MODEM_32K_EN 0x1 63 #define PER_EN 0x1 64 65 #define CPU_SUSPEND_SIZE 200 66 #define ULPD_LOW_PWR_EN 0x0001 67 #define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010 68 #define ULPD_SETUP_ANALOG_CELL_3_VAL 0 69 #define ULPD_POWER_CTRL_REG_VAL 0x0219 70 71 #define DSP_IDLE_DELAY 10 72 #define DSP_IDLE 0x0040 73 #define DSP_RST 0x0004 74 #define DSP_ENABLE 0x0002 75 #define SUFFICIENT_DSP_RESET_TIME 1000 76 #define DEFAULT_MPUI_CONFIG 0x05cf 77 #define ENABLE_XORCLK 0x2 78 #define DSP_CLOCK_ENABLE 0x2000 79 #define DSP_IDLE_MODE 0x2 80 #define TC_IDLE_REQUEST (0x0000000c) 81 82 #define IRQ_LEVEL2 (1<<0) 83 #define IRQ_KEYBOARD (1<<1) 84 #define IRQ_UART2 (1<<15) 85 86 #define PDE_BIT 0x08 87 #define PWD_EN_BIT 0x04 88 #define EN_PERCK_BIT 0x04 89 90 #define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7 91 #define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5 92 #define OMAP1510_IDLE_LOOP_REQUEST 0x0c00 93 #define OMAP1510_IDLE_CLOCK_DOMAINS 0x2 94 95 /* Both big sleep and deep sleep use same values. Difference is in ULPD. */ 96 #define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7 97 #define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7 98 #define OMAP1610_IDLECT3_VAL 0x3f 99 #define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c 100 #define OMAP1610_IDLECT3 0xfffece24 101 #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 102 103 #define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7 104 #define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7 105 #define OMAP7XX_IDLECT3_VAL 0x3f 106 #define OMAP7XX_IDLECT3 0xfffece24 107 #define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 108 109 #if !defined(CONFIG_ARCH_OMAP730) && \ 110 !defined(CONFIG_ARCH_OMAP850) && \ 111 !defined(CONFIG_ARCH_OMAP15XX) && \ 112 !defined(CONFIG_ARCH_OMAP16XX) 113 #warning "Power management for this processor not implemented yet" 114 #endif 115 116 #ifndef __ASSEMBLER__ 117 118 #include <linux/clk.h> 119 120 extern struct kset power_subsys; 121 122 extern void prevent_idle_sleep(void); 123 extern void allow_idle_sleep(void); 124 125 extern void omap1_pm_idle(void); 126 extern void omap1_pm_suspend(void); 127 128 extern void omap7xx_cpu_suspend(unsigned long, unsigned long); 129 extern void omap1510_cpu_suspend(unsigned long, unsigned long); 130 extern void omap1610_cpu_suspend(unsigned long, unsigned long); 131 extern void omap7xx_idle_loop_suspend(void); 132 extern void omap1510_idle_loop_suspend(void); 133 extern void omap1610_idle_loop_suspend(void); 134 135 extern unsigned int omap7xx_cpu_suspend_sz; 136 extern unsigned int omap1510_cpu_suspend_sz; 137 extern unsigned int omap1610_cpu_suspend_sz; 138 extern unsigned int omap7xx_idle_loop_suspend_sz; 139 extern unsigned int omap1510_idle_loop_suspend_sz; 140 extern unsigned int omap1610_idle_loop_suspend_sz; 141 142 #ifdef CONFIG_OMAP_SERIAL_WAKE 143 extern void omap_serial_wake_trigger(int enable); 144 #else 145 #define omap_serial_wakeup_init() {} 146 #define omap_serial_wake_trigger(x) {} 147 #endif /* CONFIG_OMAP_SERIAL_WAKE */ 148 149 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) 150 #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) 151 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] 152 153 #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) 154 #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) 155 #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] 156 157 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) 158 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) 159 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] 160 161 #define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x) 162 #define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x)) 163 #define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] 164 165 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) 166 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) 167 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] 168 169 #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x) 170 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) 171 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] 172 173 /* 174 * List of global OMAP registers to preserve. 175 * More ones like CP and general purpose register values are preserved 176 * with the stack pointer in sleep.S. 177 */ 178 179 enum arm_save_state { 180 ARM_SLEEP_SAVE_START = 0, 181 /* 182 * MPU control registers 32 bits 183 */ 184 ARM_SLEEP_SAVE_ARM_CKCTL, 185 ARM_SLEEP_SAVE_ARM_IDLECT1, 186 ARM_SLEEP_SAVE_ARM_IDLECT2, 187 ARM_SLEEP_SAVE_ARM_IDLECT3, 188 ARM_SLEEP_SAVE_ARM_EWUPCT, 189 ARM_SLEEP_SAVE_ARM_RSTCT1, 190 ARM_SLEEP_SAVE_ARM_RSTCT2, 191 ARM_SLEEP_SAVE_ARM_SYSST, 192 ARM_SLEEP_SAVE_SIZE 193 }; 194 195 enum dsp_save_state { 196 DSP_SLEEP_SAVE_START = 0, 197 /* 198 * DSP registers 16 bits 199 */ 200 DSP_SLEEP_SAVE_DSP_IDLECT2, 201 DSP_SLEEP_SAVE_SIZE 202 }; 203 204 enum ulpd_save_state { 205 ULPD_SLEEP_SAVE_START = 0, 206 /* 207 * ULPD registers 16 bits 208 */ 209 ULPD_SLEEP_SAVE_ULPD_IT_STATUS, 210 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL, 211 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ, 212 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ, 213 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL, 214 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL, 215 ULPD_SLEEP_SAVE_SIZE 216 }; 217 218 enum mpui1510_save_state { 219 MPUI1510_SLEEP_SAVE_START = 0, 220 /* 221 * MPUI registers 32 bits 222 */ 223 MPUI1510_SLEEP_SAVE_MPUI_CTRL, 224 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 225 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 226 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS, 227 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 228 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, 229 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, 230 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, 231 #if defined(CONFIG_ARCH_OMAP15XX) 232 MPUI1510_SLEEP_SAVE_SIZE 233 #else 234 MPUI1510_SLEEP_SAVE_SIZE = 0 235 #endif 236 }; 237 238 enum mpui7xx_save_state { 239 MPUI7XX_SLEEP_SAVE_START = 0, 240 /* 241 * MPUI registers 32 bits 242 */ 243 MPUI7XX_SLEEP_SAVE_MPUI_CTRL, 244 MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 245 MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 246 MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS, 247 MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 248 MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG, 249 MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR, 250 MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR, 251 MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR, 252 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 253 MPUI7XX_SLEEP_SAVE_SIZE 254 #else 255 MPUI7XX_SLEEP_SAVE_SIZE = 0 256 #endif 257 }; 258 259 enum mpui1610_save_state { 260 MPUI1610_SLEEP_SAVE_START = 0, 261 /* 262 * MPUI registers 32 bits 263 */ 264 MPUI1610_SLEEP_SAVE_MPUI_CTRL, 265 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 266 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 267 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS, 268 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 269 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG, 270 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR, 271 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR, 272 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR, 273 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR, 274 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR, 275 #if defined(CONFIG_ARCH_OMAP16XX) 276 MPUI1610_SLEEP_SAVE_SIZE 277 #else 278 MPUI1610_SLEEP_SAVE_SIZE = 0 279 #endif 280 }; 281 282 #endif /* ASSEMBLER */ 283 #endif /* __ASM_ARCH_OMAP_PM_H */ 284