1 /* 2 * linux/arch/arm/mach-omap1/pm.c 3 * 4 * OMAP Power Management Routines 5 * 6 * Original code for the SA11x0: 7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 8 * 9 * Modified for the PXA250 by Nicolas Pitre: 10 * Copyright (c) 2002 Monta Vista Software, Inc. 11 * 12 * Modified for the OMAP1510 by David Singleton: 13 * Copyright (c) 2002 Monta Vista Software, Inc. 14 * 15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 * 22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * You should have received a copy of the GNU General Public License along 34 * with this program; if not, write to the Free Software Foundation, Inc., 35 * 675 Mass Ave, Cambridge, MA 02139, USA. 36 */ 37 38 #include <linux/suspend.h> 39 #include <linux/sched.h> 40 #include <linux/debugfs.h> 41 #include <linux/seq_file.h> 42 #include <linux/interrupt.h> 43 #include <linux/sysfs.h> 44 #include <linux/module.h> 45 #include <linux/io.h> 46 #include <linux/atomic.h> 47 #include <linux/cpu.h> 48 49 #include <asm/fncpy.h> 50 #include <asm/system_misc.h> 51 #include <asm/irq.h> 52 #include <asm/mach/time.h> 53 #include <asm/mach/irq.h> 54 55 #include <mach/tc.h> 56 #include <mach/mux.h> 57 #include <linux/omap-dma.h> 58 #include <plat/dmtimer.h> 59 60 #include <mach/irqs.h> 61 62 #include "iomap.h" 63 #include "clock.h" 64 #include "pm.h" 65 #include "sram.h" 66 67 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 68 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; 69 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; 70 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; 71 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 72 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 73 74 static unsigned short enable_dyn_sleep; 75 76 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, 77 char *buf) 78 { 79 return sprintf(buf, "%hu\n", enable_dyn_sleep); 80 } 81 82 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, 83 const char * buf, size_t n) 84 { 85 unsigned short value; 86 if (sscanf(buf, "%hu", &value) != 1 || 87 (value != 0 && value != 1) || 88 (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) { 89 pr_err("idle_sleep_store: Invalid value\n"); 90 return -EINVAL; 91 } 92 enable_dyn_sleep = value; 93 return n; 94 } 95 96 static struct kobj_attribute sleep_while_idle_attr = 97 __ATTR(sleep_while_idle, 0644, idle_show, idle_store); 98 99 100 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 101 102 /* 103 * Let's power down on idle, but only if we are really 104 * idle, because once we start down the path of 105 * going idle we continue to do idle even if we get 106 * a clock tick interrupt . . 107 */ 108 void omap1_pm_idle(void) 109 { 110 extern __u32 arm_idlect1_mask; 111 __u32 use_idlect1 = arm_idlect1_mask; 112 113 local_fiq_disable(); 114 115 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER) 116 use_idlect1 = use_idlect1 & ~(1 << 9); 117 #endif 118 119 #ifdef CONFIG_OMAP_DM_TIMER 120 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); 121 #endif 122 123 if (omap_dma_running()) 124 use_idlect1 &= ~(1 << 6); 125 126 /* 127 * We should be able to remove the do_sleep variable and multiple 128 * tests above as soon as drivers, timer and DMA code have been fixed. 129 * Even the sleep block count should become obsolete. 130 */ 131 if ((use_idlect1 != ~0) || !enable_dyn_sleep) { 132 133 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); 134 if (cpu_is_omap15xx()) 135 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; 136 else 137 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; 138 omap_writel(use_idlect1, ARM_IDLECT1); 139 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); 140 omap_writel(saved_idlect1, ARM_IDLECT1); 141 142 local_fiq_enable(); 143 return; 144 } 145 omap_sram_suspend(omap_readl(ARM_IDLECT1), 146 omap_readl(ARM_IDLECT2)); 147 148 local_fiq_enable(); 149 } 150 151 /* 152 * Configuration of the wakeup event is board specific. For the 153 * moment we put it into this helper function. Later it may move 154 * to board specific files. 155 */ 156 static void omap_pm_wakeup_setup(void) 157 { 158 u32 level1_wake = 0; 159 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); 160 161 /* 162 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, 163 * and the L2 wakeup interrupts: keypad and UART2. Note that the 164 * drivers must still separately call omap_set_gpio_wakeup() to 165 * wake up to a GPIO interrupt. 166 */ 167 if (cpu_is_omap7xx()) 168 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | 169 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); 170 else if (cpu_is_omap15xx()) 171 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 172 OMAP_IRQ_BIT(INT_1510_IH2_IRQ); 173 else if (cpu_is_omap16xx()) 174 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 175 OMAP_IRQ_BIT(INT_1610_IH2_IRQ); 176 177 omap_writel(~level1_wake, OMAP_IH1_MIR); 178 179 if (cpu_is_omap7xx()) { 180 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 181 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | 182 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), 183 OMAP_IH2_1_MIR); 184 } else if (cpu_is_omap15xx()) { 185 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 186 omap_writel(~level2_wake, OMAP_IH2_MIR); 187 } else if (cpu_is_omap16xx()) { 188 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 189 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 190 191 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ 192 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), 193 OMAP_IH2_1_MIR); 194 omap_writel(~0x0, OMAP_IH2_2_MIR); 195 omap_writel(~0x0, OMAP_IH2_3_MIR); 196 } 197 198 /* New IRQ agreement, recalculate in cascade order */ 199 omap_writel(1, OMAP_IH2_CONTROL); 200 omap_writel(1, OMAP_IH1_CONTROL); 201 } 202 203 #define EN_DSPCK 13 /* ARM_CKCTL */ 204 #define EN_APICK 6 /* ARM_IDLECT2 */ 205 #define DSP_EN 1 /* ARM_RSTCT1 */ 206 207 void omap1_pm_suspend(void) 208 { 209 unsigned long arg0 = 0, arg1 = 0; 210 211 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n", 212 omap_rev()); 213 214 omap_serial_wake_trigger(1); 215 216 if (!cpu_is_omap15xx()) 217 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); 218 219 /* 220 * Step 1: turn off interrupts (FIXME: NOTE: already disabled) 221 */ 222 223 local_irq_disable(); 224 local_fiq_disable(); 225 226 /* 227 * Step 2: save registers 228 * 229 * The omap is a strange/beautiful device. The caches, memory 230 * and register state are preserved across power saves. 231 * We have to save and restore very little register state to 232 * idle the omap. 233 * 234 * Save interrupt, MPUI, ARM and UPLD control registers. 235 */ 236 237 if (cpu_is_omap7xx()) { 238 MPUI7XX_SAVE(OMAP_IH1_MIR); 239 MPUI7XX_SAVE(OMAP_IH2_0_MIR); 240 MPUI7XX_SAVE(OMAP_IH2_1_MIR); 241 MPUI7XX_SAVE(MPUI_CTRL); 242 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); 243 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); 244 MPUI7XX_SAVE(EMIFS_CONFIG); 245 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); 246 247 } else if (cpu_is_omap15xx()) { 248 MPUI1510_SAVE(OMAP_IH1_MIR); 249 MPUI1510_SAVE(OMAP_IH2_MIR); 250 MPUI1510_SAVE(MPUI_CTRL); 251 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 252 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 253 MPUI1510_SAVE(EMIFS_CONFIG); 254 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 255 } else if (cpu_is_omap16xx()) { 256 MPUI1610_SAVE(OMAP_IH1_MIR); 257 MPUI1610_SAVE(OMAP_IH2_0_MIR); 258 MPUI1610_SAVE(OMAP_IH2_1_MIR); 259 MPUI1610_SAVE(OMAP_IH2_2_MIR); 260 MPUI1610_SAVE(OMAP_IH2_3_MIR); 261 MPUI1610_SAVE(MPUI_CTRL); 262 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 263 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 264 MPUI1610_SAVE(EMIFS_CONFIG); 265 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 266 } 267 268 ARM_SAVE(ARM_CKCTL); 269 ARM_SAVE(ARM_IDLECT1); 270 ARM_SAVE(ARM_IDLECT2); 271 if (!(cpu_is_omap15xx())) 272 ARM_SAVE(ARM_IDLECT3); 273 ARM_SAVE(ARM_EWUPCT); 274 ARM_SAVE(ARM_RSTCT1); 275 ARM_SAVE(ARM_RSTCT2); 276 ARM_SAVE(ARM_SYSST); 277 ULPD_SAVE(ULPD_CLOCK_CTRL); 278 ULPD_SAVE(ULPD_STATUS_REQ); 279 280 /* (Step 3 removed - we now allow deep sleep by default) */ 281 282 /* 283 * Step 4: OMAP DSP Shutdown 284 */ 285 286 /* stop DSP */ 287 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); 288 289 /* shut down dsp_ck */ 290 if (!cpu_is_omap7xx()) 291 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 292 293 /* temporarily enabling api_ck to access DSP registers */ 294 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 295 296 /* save DSP registers */ 297 DSP_SAVE(DSP_IDLECT2); 298 299 /* Stop all DSP domain clocks */ 300 __raw_writew(0, DSP_IDLECT2); 301 302 /* 303 * Step 5: Wakeup Event Setup 304 */ 305 306 omap_pm_wakeup_setup(); 307 308 /* 309 * Step 6: ARM and Traffic controller shutdown 310 */ 311 312 /* disable ARM watchdog */ 313 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); 314 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); 315 316 /* 317 * Step 6b: ARM and Traffic controller shutdown 318 * 319 * Step 6 continues here. Prepare jump to power management 320 * assembly code in internal SRAM. 321 * 322 * Since the omap_cpu_suspend routine has been copied to 323 * SRAM, we'll do an indirect procedure call to it and pass the 324 * contents of arm_idlect1 and arm_idlect2 so it can restore 325 * them when it wakes up and it will return. 326 */ 327 328 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; 329 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; 330 331 /* 332 * Step 6c: ARM and Traffic controller shutdown 333 * 334 * Jump to assembly code. The processor will stay there 335 * until wake up. 336 */ 337 omap_sram_suspend(arg0, arg1); 338 339 /* 340 * If we are here, processor is woken up! 341 */ 342 343 /* 344 * Restore DSP clocks 345 */ 346 347 /* again temporarily enabling api_ck to access DSP registers */ 348 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 349 350 /* Restore DSP domain clocks */ 351 DSP_RESTORE(DSP_IDLECT2); 352 353 /* 354 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did 355 */ 356 357 if (!(cpu_is_omap15xx())) 358 ARM_RESTORE(ARM_IDLECT3); 359 ARM_RESTORE(ARM_CKCTL); 360 ARM_RESTORE(ARM_EWUPCT); 361 ARM_RESTORE(ARM_RSTCT1); 362 ARM_RESTORE(ARM_RSTCT2); 363 ARM_RESTORE(ARM_SYSST); 364 ULPD_RESTORE(ULPD_CLOCK_CTRL); 365 ULPD_RESTORE(ULPD_STATUS_REQ); 366 367 if (cpu_is_omap7xx()) { 368 MPUI7XX_RESTORE(EMIFS_CONFIG); 369 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); 370 MPUI7XX_RESTORE(OMAP_IH1_MIR); 371 MPUI7XX_RESTORE(OMAP_IH2_0_MIR); 372 MPUI7XX_RESTORE(OMAP_IH2_1_MIR); 373 } else if (cpu_is_omap15xx()) { 374 MPUI1510_RESTORE(MPUI_CTRL); 375 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); 376 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); 377 MPUI1510_RESTORE(EMIFS_CONFIG); 378 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); 379 MPUI1510_RESTORE(OMAP_IH1_MIR); 380 MPUI1510_RESTORE(OMAP_IH2_MIR); 381 } else if (cpu_is_omap16xx()) { 382 MPUI1610_RESTORE(MPUI_CTRL); 383 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); 384 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); 385 MPUI1610_RESTORE(EMIFS_CONFIG); 386 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); 387 388 MPUI1610_RESTORE(OMAP_IH1_MIR); 389 MPUI1610_RESTORE(OMAP_IH2_0_MIR); 390 MPUI1610_RESTORE(OMAP_IH2_1_MIR); 391 MPUI1610_RESTORE(OMAP_IH2_2_MIR); 392 MPUI1610_RESTORE(OMAP_IH2_3_MIR); 393 } 394 395 if (!cpu_is_omap15xx()) 396 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); 397 398 /* 399 * Re-enable interrupts 400 */ 401 402 local_irq_enable(); 403 local_fiq_enable(); 404 405 omap_serial_wake_trigger(0); 406 407 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n", 408 omap_rev()); 409 } 410 411 #ifdef CONFIG_DEBUG_FS 412 /* 413 * Read system PM registers for debugging 414 */ 415 static int omap_pm_debug_show(struct seq_file *m, void *v) 416 { 417 ARM_SAVE(ARM_CKCTL); 418 ARM_SAVE(ARM_IDLECT1); 419 ARM_SAVE(ARM_IDLECT2); 420 if (!(cpu_is_omap15xx())) 421 ARM_SAVE(ARM_IDLECT3); 422 ARM_SAVE(ARM_EWUPCT); 423 ARM_SAVE(ARM_RSTCT1); 424 ARM_SAVE(ARM_RSTCT2); 425 ARM_SAVE(ARM_SYSST); 426 427 ULPD_SAVE(ULPD_IT_STATUS); 428 ULPD_SAVE(ULPD_CLOCK_CTRL); 429 ULPD_SAVE(ULPD_SOFT_REQ); 430 ULPD_SAVE(ULPD_STATUS_REQ); 431 ULPD_SAVE(ULPD_DPLL_CTRL); 432 ULPD_SAVE(ULPD_POWER_CTRL); 433 434 if (cpu_is_omap7xx()) { 435 MPUI7XX_SAVE(MPUI_CTRL); 436 MPUI7XX_SAVE(MPUI_DSP_STATUS); 437 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); 438 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); 439 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); 440 MPUI7XX_SAVE(EMIFS_CONFIG); 441 } else if (cpu_is_omap15xx()) { 442 MPUI1510_SAVE(MPUI_CTRL); 443 MPUI1510_SAVE(MPUI_DSP_STATUS); 444 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 445 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 446 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 447 MPUI1510_SAVE(EMIFS_CONFIG); 448 } else if (cpu_is_omap16xx()) { 449 MPUI1610_SAVE(MPUI_CTRL); 450 MPUI1610_SAVE(MPUI_DSP_STATUS); 451 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 452 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 453 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 454 MPUI1610_SAVE(EMIFS_CONFIG); 455 } 456 457 seq_printf(m, 458 "ARM_CKCTL_REG: 0x%-8x \n" 459 "ARM_IDLECT1_REG: 0x%-8x \n" 460 "ARM_IDLECT2_REG: 0x%-8x \n" 461 "ARM_IDLECT3_REG: 0x%-8x \n" 462 "ARM_EWUPCT_REG: 0x%-8x \n" 463 "ARM_RSTCT1_REG: 0x%-8x \n" 464 "ARM_RSTCT2_REG: 0x%-8x \n" 465 "ARM_SYSST_REG: 0x%-8x \n" 466 "ULPD_IT_STATUS_REG: 0x%-4x \n" 467 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n" 468 "ULPD_SOFT_REQ_REG: 0x%-4x \n" 469 "ULPD_DPLL_CTRL_REG: 0x%-4x \n" 470 "ULPD_STATUS_REQ_REG: 0x%-4x \n" 471 "ULPD_POWER_CTRL_REG: 0x%-4x \n", 472 ARM_SHOW(ARM_CKCTL), 473 ARM_SHOW(ARM_IDLECT1), 474 ARM_SHOW(ARM_IDLECT2), 475 ARM_SHOW(ARM_IDLECT3), 476 ARM_SHOW(ARM_EWUPCT), 477 ARM_SHOW(ARM_RSTCT1), 478 ARM_SHOW(ARM_RSTCT2), 479 ARM_SHOW(ARM_SYSST), 480 ULPD_SHOW(ULPD_IT_STATUS), 481 ULPD_SHOW(ULPD_CLOCK_CTRL), 482 ULPD_SHOW(ULPD_SOFT_REQ), 483 ULPD_SHOW(ULPD_DPLL_CTRL), 484 ULPD_SHOW(ULPD_STATUS_REQ), 485 ULPD_SHOW(ULPD_POWER_CTRL)); 486 487 if (cpu_is_omap7xx()) { 488 seq_printf(m, 489 "MPUI7XX_CTRL_REG 0x%-8x \n" 490 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" 491 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 492 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" 493 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" 494 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", 495 MPUI7XX_SHOW(MPUI_CTRL), 496 MPUI7XX_SHOW(MPUI_DSP_STATUS), 497 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), 498 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), 499 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), 500 MPUI7XX_SHOW(EMIFS_CONFIG)); 501 } else if (cpu_is_omap15xx()) { 502 seq_printf(m, 503 "MPUI1510_CTRL_REG 0x%-8x \n" 504 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" 505 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 506 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" 507 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" 508 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n", 509 MPUI1510_SHOW(MPUI_CTRL), 510 MPUI1510_SHOW(MPUI_DSP_STATUS), 511 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), 512 MPUI1510_SHOW(MPUI_DSP_API_CONFIG), 513 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), 514 MPUI1510_SHOW(EMIFS_CONFIG)); 515 } else if (cpu_is_omap16xx()) { 516 seq_printf(m, 517 "MPUI1610_CTRL_REG 0x%-8x \n" 518 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n" 519 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 520 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" 521 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" 522 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n", 523 MPUI1610_SHOW(MPUI_CTRL), 524 MPUI1610_SHOW(MPUI_DSP_STATUS), 525 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), 526 MPUI1610_SHOW(MPUI_DSP_API_CONFIG), 527 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), 528 MPUI1610_SHOW(EMIFS_CONFIG)); 529 } 530 531 return 0; 532 } 533 534 static int omap_pm_debug_open(struct inode *inode, struct file *file) 535 { 536 return single_open(file, omap_pm_debug_show, 537 &inode->i_private); 538 } 539 540 static const struct file_operations omap_pm_debug_fops = { 541 .open = omap_pm_debug_open, 542 .read = seq_read, 543 .llseek = seq_lseek, 544 .release = single_release, 545 }; 546 547 static void omap_pm_init_debugfs(void) 548 { 549 struct dentry *d; 550 551 d = debugfs_create_dir("pm_debug", NULL); 552 if (!d) 553 return; 554 555 (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, 556 d, NULL, &omap_pm_debug_fops); 557 } 558 559 #endif /* CONFIG_DEBUG_FS */ 560 561 /* 562 * omap_pm_prepare - Do preliminary suspend work. 563 * 564 */ 565 static int omap_pm_prepare(void) 566 { 567 /* We cannot sleep in idle until we have resumed */ 568 cpu_idle_poll_ctrl(true); 569 return 0; 570 } 571 572 573 /* 574 * omap_pm_enter - Actually enter a sleep state. 575 * @state: State we're entering. 576 * 577 */ 578 579 static int omap_pm_enter(suspend_state_t state) 580 { 581 switch (state) 582 { 583 case PM_SUSPEND_STANDBY: 584 case PM_SUSPEND_MEM: 585 omap1_pm_suspend(); 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 return 0; 592 } 593 594 595 /** 596 * omap_pm_finish - Finish up suspend sequence. 597 * 598 * This is called after we wake back up (or if entering the sleep state 599 * failed). 600 */ 601 602 static void omap_pm_finish(void) 603 { 604 cpu_idle_poll_ctrl(false); 605 } 606 607 608 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) 609 { 610 return IRQ_HANDLED; 611 } 612 613 static struct irqaction omap_wakeup_irq = { 614 .name = "peripheral wakeup", 615 .handler = omap_wakeup_interrupt 616 }; 617 618 619 620 static const struct platform_suspend_ops omap_pm_ops = { 621 .prepare = omap_pm_prepare, 622 .enter = omap_pm_enter, 623 .finish = omap_pm_finish, 624 .valid = suspend_valid_only_mem, 625 }; 626 627 static int __init omap_pm_init(void) 628 { 629 int error = 0; 630 631 if (!cpu_class_is_omap1()) 632 return -ENODEV; 633 634 pr_info("Power Management for TI OMAP.\n"); 635 636 if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER)) 637 pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n"); 638 639 if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER)) 640 pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n"); 641 642 if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) && 643 IS_ENABLED(CONFIG_OMAP_DM_TIMER)) { 644 /* OMAP16xx only */ 645 pr_info("OMAP1 PM: sleep states in idle enabled\n"); 646 enable_dyn_sleep = 1; 647 } 648 649 /* 650 * We copy the assembler sleep/wakeup routines to SRAM. 651 * These routines need to be in SRAM as that's the only 652 * memory the MPU can see when it wakes up. 653 */ 654 if (cpu_is_omap7xx()) { 655 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, 656 omap7xx_cpu_suspend_sz); 657 } else if (cpu_is_omap15xx()) { 658 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 659 omap1510_cpu_suspend_sz); 660 } else if (cpu_is_omap16xx()) { 661 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, 662 omap1610_cpu_suspend_sz); 663 } 664 665 if (omap_sram_suspend == NULL) { 666 printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); 667 return -ENODEV; 668 } 669 670 arm_pm_idle = omap1_pm_idle; 671 672 if (cpu_is_omap7xx()) 673 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq); 674 else if (cpu_is_omap16xx()) 675 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); 676 677 /* Program new power ramp-up time 678 * (0 for most boards since we don't lower voltage when in deep sleep) 679 */ 680 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); 681 682 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ 683 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); 684 685 /* Configure IDLECT3 */ 686 if (cpu_is_omap7xx()) 687 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); 688 else if (cpu_is_omap16xx()) 689 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); 690 691 suspend_set_ops(&omap_pm_ops); 692 693 #ifdef CONFIG_DEBUG_FS 694 omap_pm_init_debugfs(); 695 #endif 696 697 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); 698 if (error) 699 printk(KERN_ERR "sysfs_create_file failed: %d\n", error); 700 701 if (cpu_is_omap16xx()) { 702 /* configure LOW_PWR pin */ 703 omap_cfg_reg(T20_1610_LOW_PWR); 704 } 705 706 return error; 707 } 708 __initcall(omap_pm_init); 709