1 /* 2 * linux/arch/arm/mach-omap1/pm.c 3 * 4 * OMAP Power Management Routines 5 * 6 * Original code for the SA11x0: 7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 8 * 9 * Modified for the PXA250 by Nicolas Pitre: 10 * Copyright (c) 2002 Monta Vista Software, Inc. 11 * 12 * Modified for the OMAP1510 by David Singleton: 13 * Copyright (c) 2002 Monta Vista Software, Inc. 14 * 15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 * 22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * You should have received a copy of the GNU General Public License along 34 * with this program; if not, write to the Free Software Foundation, Inc., 35 * 675 Mass Ave, Cambridge, MA 02139, USA. 36 */ 37 38 #include <linux/suspend.h> 39 #include <linux/sched.h> 40 #include <linux/proc_fs.h> 41 #include <linux/interrupt.h> 42 #include <linux/sysfs.h> 43 #include <linux/module.h> 44 45 #include <asm/io.h> 46 #include <asm/irq.h> 47 #include <asm/atomic.h> 48 #include <asm/mach/time.h> 49 #include <asm/mach/irq.h> 50 #include <asm/mach-types.h> 51 52 #include <asm/arch/cpu.h> 53 #include <asm/arch/irqs.h> 54 #include <asm/arch/clock.h> 55 #include <asm/arch/sram.h> 56 #include <asm/arch/tc.h> 57 #include <asm/arch/pm.h> 58 #include <asm/arch/mux.h> 59 #include <asm/arch/dma.h> 60 #include <asm/arch/dmtimer.h> 61 62 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 63 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; 64 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; 65 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; 66 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 67 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 68 69 #ifdef CONFIG_OMAP_32K_TIMER 70 71 static unsigned short enable_dyn_sleep = 1; 72 73 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, 74 char *buf) 75 { 76 return sprintf(buf, "%hu\n", enable_dyn_sleep); 77 } 78 79 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, 80 const char * buf, size_t n) 81 { 82 unsigned short value; 83 if (sscanf(buf, "%hu", &value) != 1 || 84 (value != 0 && value != 1)) { 85 printk(KERN_ERR "idle_sleep_store: Invalid value\n"); 86 return -EINVAL; 87 } 88 enable_dyn_sleep = value; 89 return n; 90 } 91 92 static struct kobj_attribute sleep_while_idle_attr = 93 __ATTR(sleep_while_idle, 0644, idle_show, idle_store); 94 95 #endif 96 97 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 98 99 /* 100 * Let's power down on idle, but only if we are really 101 * idle, because once we start down the path of 102 * going idle we continue to do idle even if we get 103 * a clock tick interrupt . . 104 */ 105 void omap_pm_idle(void) 106 { 107 extern __u32 arm_idlect1_mask; 108 __u32 use_idlect1 = arm_idlect1_mask; 109 int do_sleep = 0; 110 111 local_irq_disable(); 112 local_fiq_disable(); 113 if (need_resched()) { 114 local_fiq_enable(); 115 local_irq_enable(); 116 return; 117 } 118 119 /* 120 * Since an interrupt may set up a timer, we don't want to 121 * reprogram the hardware timer with interrupts enabled. 122 * Re-enable interrupts only after returning from idle. 123 */ 124 timer_dyn_reprogram(); 125 126 #ifdef CONFIG_OMAP_MPU_TIMER 127 #warning Enable 32kHz OS timer in order to allow sleep states in idle 128 use_idlect1 = use_idlect1 & ~(1 << 9); 129 #else 130 131 while (enable_dyn_sleep) { 132 133 #ifdef CONFIG_CBUS_TAHVO_USB 134 extern int vbus_active; 135 /* Clock requirements? */ 136 if (vbus_active) 137 break; 138 #endif 139 do_sleep = 1; 140 break; 141 } 142 143 #endif 144 145 #ifdef CONFIG_OMAP_DM_TIMER 146 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); 147 #endif 148 149 if (omap_dma_running()) 150 use_idlect1 &= ~(1 << 6); 151 152 /* We should be able to remove the do_sleep variable and multiple 153 * tests above as soon as drivers, timer and DMA code have been fixed. 154 * Even the sleep block count should become obsolete. */ 155 if ((use_idlect1 != ~0) || !do_sleep) { 156 157 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); 158 if (cpu_is_omap15xx()) 159 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; 160 else 161 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; 162 omap_writel(use_idlect1, ARM_IDLECT1); 163 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); 164 omap_writel(saved_idlect1, ARM_IDLECT1); 165 166 local_fiq_enable(); 167 local_irq_enable(); 168 return; 169 } 170 omap_sram_suspend(omap_readl(ARM_IDLECT1), 171 omap_readl(ARM_IDLECT2)); 172 173 local_fiq_enable(); 174 local_irq_enable(); 175 } 176 177 /* 178 * Configuration of the wakeup event is board specific. For the 179 * moment we put it into this helper function. Later it may move 180 * to board specific files. 181 */ 182 static void omap_pm_wakeup_setup(void) 183 { 184 u32 level1_wake = 0; 185 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); 186 187 /* 188 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, 189 * and the L2 wakeup interrupts: keypad and UART2. Note that the 190 * drivers must still separately call omap_set_gpio_wakeup() to 191 * wake up to a GPIO interrupt. 192 */ 193 if (cpu_is_omap730()) 194 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) | 195 OMAP_IRQ_BIT(INT_730_IH2_IRQ); 196 else if (cpu_is_omap15xx()) 197 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 198 OMAP_IRQ_BIT(INT_1510_IH2_IRQ); 199 else if (cpu_is_omap16xx()) 200 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 201 OMAP_IRQ_BIT(INT_1610_IH2_IRQ); 202 203 omap_writel(~level1_wake, OMAP_IH1_MIR); 204 205 if (cpu_is_omap730()) { 206 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 207 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | 208 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), 209 OMAP_IH2_1_MIR); 210 } else if (cpu_is_omap15xx()) { 211 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 212 omap_writel(~level2_wake, OMAP_IH2_MIR); 213 } else if (cpu_is_omap16xx()) { 214 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 215 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 216 217 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ 218 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), 219 OMAP_IH2_1_MIR); 220 omap_writel(~0x0, OMAP_IH2_2_MIR); 221 omap_writel(~0x0, OMAP_IH2_3_MIR); 222 } 223 224 /* New IRQ agreement, recalculate in cascade order */ 225 omap_writel(1, OMAP_IH2_CONTROL); 226 omap_writel(1, OMAP_IH1_CONTROL); 227 } 228 229 #define EN_DSPCK 13 /* ARM_CKCTL */ 230 #define EN_APICK 6 /* ARM_IDLECT2 */ 231 #define DSP_EN 1 /* ARM_RSTCT1 */ 232 233 void omap_pm_suspend(void) 234 { 235 unsigned long arg0 = 0, arg1 = 0; 236 237 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev); 238 239 omap_serial_wake_trigger(1); 240 241 if (!cpu_is_omap15xx()) 242 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); 243 244 /* 245 * Step 1: turn off interrupts (FIXME: NOTE: already disabled) 246 */ 247 248 local_irq_disable(); 249 local_fiq_disable(); 250 251 /* 252 * Step 2: save registers 253 * 254 * The omap is a strange/beautiful device. The caches, memory 255 * and register state are preserved across power saves. 256 * We have to save and restore very little register state to 257 * idle the omap. 258 * 259 * Save interrupt, MPUI, ARM and UPLD control registers. 260 */ 261 262 if (cpu_is_omap730()) { 263 MPUI730_SAVE(OMAP_IH1_MIR); 264 MPUI730_SAVE(OMAP_IH2_0_MIR); 265 MPUI730_SAVE(OMAP_IH2_1_MIR); 266 MPUI730_SAVE(MPUI_CTRL); 267 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 268 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 269 MPUI730_SAVE(EMIFS_CONFIG); 270 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 271 272 } else if (cpu_is_omap15xx()) { 273 MPUI1510_SAVE(OMAP_IH1_MIR); 274 MPUI1510_SAVE(OMAP_IH2_MIR); 275 MPUI1510_SAVE(MPUI_CTRL); 276 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 277 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 278 MPUI1510_SAVE(EMIFS_CONFIG); 279 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 280 } else if (cpu_is_omap16xx()) { 281 MPUI1610_SAVE(OMAP_IH1_MIR); 282 MPUI1610_SAVE(OMAP_IH2_0_MIR); 283 MPUI1610_SAVE(OMAP_IH2_1_MIR); 284 MPUI1610_SAVE(OMAP_IH2_2_MIR); 285 MPUI1610_SAVE(OMAP_IH2_3_MIR); 286 MPUI1610_SAVE(MPUI_CTRL); 287 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 288 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 289 MPUI1610_SAVE(EMIFS_CONFIG); 290 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 291 } 292 293 ARM_SAVE(ARM_CKCTL); 294 ARM_SAVE(ARM_IDLECT1); 295 ARM_SAVE(ARM_IDLECT2); 296 if (!(cpu_is_omap15xx())) 297 ARM_SAVE(ARM_IDLECT3); 298 ARM_SAVE(ARM_EWUPCT); 299 ARM_SAVE(ARM_RSTCT1); 300 ARM_SAVE(ARM_RSTCT2); 301 ARM_SAVE(ARM_SYSST); 302 ULPD_SAVE(ULPD_CLOCK_CTRL); 303 ULPD_SAVE(ULPD_STATUS_REQ); 304 305 /* (Step 3 removed - we now allow deep sleep by default) */ 306 307 /* 308 * Step 4: OMAP DSP Shutdown 309 */ 310 311 /* stop DSP */ 312 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); 313 314 /* shut down dsp_ck */ 315 if (!cpu_is_omap730()) 316 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 317 318 /* temporarily enabling api_ck to access DSP registers */ 319 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 320 321 /* save DSP registers */ 322 DSP_SAVE(DSP_IDLECT2); 323 324 /* Stop all DSP domain clocks */ 325 __raw_writew(0, DSP_IDLECT2); 326 327 /* 328 * Step 5: Wakeup Event Setup 329 */ 330 331 omap_pm_wakeup_setup(); 332 333 /* 334 * Step 6: ARM and Traffic controller shutdown 335 */ 336 337 /* disable ARM watchdog */ 338 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); 339 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); 340 341 /* 342 * Step 6b: ARM and Traffic controller shutdown 343 * 344 * Step 6 continues here. Prepare jump to power management 345 * assembly code in internal SRAM. 346 * 347 * Since the omap_cpu_suspend routine has been copied to 348 * SRAM, we'll do an indirect procedure call to it and pass the 349 * contents of arm_idlect1 and arm_idlect2 so it can restore 350 * them when it wakes up and it will return. 351 */ 352 353 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; 354 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; 355 356 /* 357 * Step 6c: ARM and Traffic controller shutdown 358 * 359 * Jump to assembly code. The processor will stay there 360 * until wake up. 361 */ 362 omap_sram_suspend(arg0, arg1); 363 364 /* 365 * If we are here, processor is woken up! 366 */ 367 368 /* 369 * Restore DSP clocks 370 */ 371 372 /* again temporarily enabling api_ck to access DSP registers */ 373 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 374 375 /* Restore DSP domain clocks */ 376 DSP_RESTORE(DSP_IDLECT2); 377 378 /* 379 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did 380 */ 381 382 if (!(cpu_is_omap15xx())) 383 ARM_RESTORE(ARM_IDLECT3); 384 ARM_RESTORE(ARM_CKCTL); 385 ARM_RESTORE(ARM_EWUPCT); 386 ARM_RESTORE(ARM_RSTCT1); 387 ARM_RESTORE(ARM_RSTCT2); 388 ARM_RESTORE(ARM_SYSST); 389 ULPD_RESTORE(ULPD_CLOCK_CTRL); 390 ULPD_RESTORE(ULPD_STATUS_REQ); 391 392 if (cpu_is_omap730()) { 393 MPUI730_RESTORE(EMIFS_CONFIG); 394 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG); 395 MPUI730_RESTORE(OMAP_IH1_MIR); 396 MPUI730_RESTORE(OMAP_IH2_0_MIR); 397 MPUI730_RESTORE(OMAP_IH2_1_MIR); 398 } else if (cpu_is_omap15xx()) { 399 MPUI1510_RESTORE(MPUI_CTRL); 400 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); 401 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); 402 MPUI1510_RESTORE(EMIFS_CONFIG); 403 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); 404 MPUI1510_RESTORE(OMAP_IH1_MIR); 405 MPUI1510_RESTORE(OMAP_IH2_MIR); 406 } else if (cpu_is_omap16xx()) { 407 MPUI1610_RESTORE(MPUI_CTRL); 408 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); 409 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); 410 MPUI1610_RESTORE(EMIFS_CONFIG); 411 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); 412 413 MPUI1610_RESTORE(OMAP_IH1_MIR); 414 MPUI1610_RESTORE(OMAP_IH2_0_MIR); 415 MPUI1610_RESTORE(OMAP_IH2_1_MIR); 416 MPUI1610_RESTORE(OMAP_IH2_2_MIR); 417 MPUI1610_RESTORE(OMAP_IH2_3_MIR); 418 } 419 420 if (!cpu_is_omap15xx()) 421 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); 422 423 /* 424 * Re-enable interrupts 425 */ 426 427 local_irq_enable(); 428 local_fiq_enable(); 429 430 omap_serial_wake_trigger(0); 431 432 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev); 433 } 434 435 #if defined(DEBUG) && defined(CONFIG_PROC_FS) 436 static int g_read_completed; 437 438 /* 439 * Read system PM registers for debugging 440 */ 441 static int omap_pm_read_proc( 442 char *page_buffer, 443 char **my_first_byte, 444 off_t virtual_start, 445 int length, 446 int *eof, 447 void *data) 448 { 449 int my_buffer_offset = 0; 450 char * const my_base = page_buffer; 451 452 ARM_SAVE(ARM_CKCTL); 453 ARM_SAVE(ARM_IDLECT1); 454 ARM_SAVE(ARM_IDLECT2); 455 if (!(cpu_is_omap15xx())) 456 ARM_SAVE(ARM_IDLECT3); 457 ARM_SAVE(ARM_EWUPCT); 458 ARM_SAVE(ARM_RSTCT1); 459 ARM_SAVE(ARM_RSTCT2); 460 ARM_SAVE(ARM_SYSST); 461 462 ULPD_SAVE(ULPD_IT_STATUS); 463 ULPD_SAVE(ULPD_CLOCK_CTRL); 464 ULPD_SAVE(ULPD_SOFT_REQ); 465 ULPD_SAVE(ULPD_STATUS_REQ); 466 ULPD_SAVE(ULPD_DPLL_CTRL); 467 ULPD_SAVE(ULPD_POWER_CTRL); 468 469 if (cpu_is_omap730()) { 470 MPUI730_SAVE(MPUI_CTRL); 471 MPUI730_SAVE(MPUI_DSP_STATUS); 472 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 473 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 474 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 475 MPUI730_SAVE(EMIFS_CONFIG); 476 } else if (cpu_is_omap15xx()) { 477 MPUI1510_SAVE(MPUI_CTRL); 478 MPUI1510_SAVE(MPUI_DSP_STATUS); 479 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 480 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 481 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 482 MPUI1510_SAVE(EMIFS_CONFIG); 483 } else if (cpu_is_omap16xx()) { 484 MPUI1610_SAVE(MPUI_CTRL); 485 MPUI1610_SAVE(MPUI_DSP_STATUS); 486 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 487 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 488 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 489 MPUI1610_SAVE(EMIFS_CONFIG); 490 } 491 492 if (virtual_start == 0) { 493 g_read_completed = 0; 494 495 my_buffer_offset += sprintf(my_base + my_buffer_offset, 496 "ARM_CKCTL_REG: 0x%-8x \n" 497 "ARM_IDLECT1_REG: 0x%-8x \n" 498 "ARM_IDLECT2_REG: 0x%-8x \n" 499 "ARM_IDLECT3_REG: 0x%-8x \n" 500 "ARM_EWUPCT_REG: 0x%-8x \n" 501 "ARM_RSTCT1_REG: 0x%-8x \n" 502 "ARM_RSTCT2_REG: 0x%-8x \n" 503 "ARM_SYSST_REG: 0x%-8x \n" 504 "ULPD_IT_STATUS_REG: 0x%-4x \n" 505 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n" 506 "ULPD_SOFT_REQ_REG: 0x%-4x \n" 507 "ULPD_DPLL_CTRL_REG: 0x%-4x \n" 508 "ULPD_STATUS_REQ_REG: 0x%-4x \n" 509 "ULPD_POWER_CTRL_REG: 0x%-4x \n", 510 ARM_SHOW(ARM_CKCTL), 511 ARM_SHOW(ARM_IDLECT1), 512 ARM_SHOW(ARM_IDLECT2), 513 ARM_SHOW(ARM_IDLECT3), 514 ARM_SHOW(ARM_EWUPCT), 515 ARM_SHOW(ARM_RSTCT1), 516 ARM_SHOW(ARM_RSTCT2), 517 ARM_SHOW(ARM_SYSST), 518 ULPD_SHOW(ULPD_IT_STATUS), 519 ULPD_SHOW(ULPD_CLOCK_CTRL), 520 ULPD_SHOW(ULPD_SOFT_REQ), 521 ULPD_SHOW(ULPD_DPLL_CTRL), 522 ULPD_SHOW(ULPD_STATUS_REQ), 523 ULPD_SHOW(ULPD_POWER_CTRL)); 524 525 if (cpu_is_omap730()) { 526 my_buffer_offset += sprintf(my_base + my_buffer_offset, 527 "MPUI730_CTRL_REG 0x%-8x \n" 528 "MPUI730_DSP_STATUS_REG: 0x%-8x \n" 529 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 530 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n" 531 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n" 532 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n", 533 MPUI730_SHOW(MPUI_CTRL), 534 MPUI730_SHOW(MPUI_DSP_STATUS), 535 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG), 536 MPUI730_SHOW(MPUI_DSP_API_CONFIG), 537 MPUI730_SHOW(EMIFF_SDRAM_CONFIG), 538 MPUI730_SHOW(EMIFS_CONFIG)); 539 } else if (cpu_is_omap15xx()) { 540 my_buffer_offset += sprintf(my_base + my_buffer_offset, 541 "MPUI1510_CTRL_REG 0x%-8x \n" 542 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" 543 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 544 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" 545 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" 546 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n", 547 MPUI1510_SHOW(MPUI_CTRL), 548 MPUI1510_SHOW(MPUI_DSP_STATUS), 549 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), 550 MPUI1510_SHOW(MPUI_DSP_API_CONFIG), 551 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), 552 MPUI1510_SHOW(EMIFS_CONFIG)); 553 } else if (cpu_is_omap16xx()) { 554 my_buffer_offset += sprintf(my_base + my_buffer_offset, 555 "MPUI1610_CTRL_REG 0x%-8x \n" 556 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n" 557 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 558 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" 559 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" 560 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n", 561 MPUI1610_SHOW(MPUI_CTRL), 562 MPUI1610_SHOW(MPUI_DSP_STATUS), 563 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), 564 MPUI1610_SHOW(MPUI_DSP_API_CONFIG), 565 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), 566 MPUI1610_SHOW(EMIFS_CONFIG)); 567 } 568 569 g_read_completed++; 570 } else if (g_read_completed >= 1) { 571 *eof = 1; 572 return 0; 573 } 574 g_read_completed++; 575 576 *my_first_byte = page_buffer; 577 return my_buffer_offset; 578 } 579 580 static void omap_pm_init_proc(void) 581 { 582 struct proc_dir_entry *entry; 583 584 entry = create_proc_read_entry("driver/omap_pm", 585 S_IWUSR | S_IRUGO, NULL, 586 omap_pm_read_proc, NULL); 587 } 588 589 #endif /* DEBUG && CONFIG_PROC_FS */ 590 591 static void (*saved_idle)(void) = NULL; 592 593 /* 594 * omap_pm_prepare - Do preliminary suspend work. 595 * 596 */ 597 static int omap_pm_prepare(void) 598 { 599 /* We cannot sleep in idle until we have resumed */ 600 saved_idle = pm_idle; 601 pm_idle = NULL; 602 603 return 0; 604 } 605 606 607 /* 608 * omap_pm_enter - Actually enter a sleep state. 609 * @state: State we're entering. 610 * 611 */ 612 613 static int omap_pm_enter(suspend_state_t state) 614 { 615 switch (state) 616 { 617 case PM_SUSPEND_STANDBY: 618 case PM_SUSPEND_MEM: 619 omap_pm_suspend(); 620 break; 621 default: 622 return -EINVAL; 623 } 624 625 return 0; 626 } 627 628 629 /** 630 * omap_pm_finish - Finish up suspend sequence. 631 * 632 * This is called after we wake back up (or if entering the sleep state 633 * failed). 634 */ 635 636 static void omap_pm_finish(void) 637 { 638 pm_idle = saved_idle; 639 } 640 641 642 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) 643 { 644 return IRQ_HANDLED; 645 } 646 647 static struct irqaction omap_wakeup_irq = { 648 .name = "peripheral wakeup", 649 .flags = IRQF_DISABLED, 650 .handler = omap_wakeup_interrupt 651 }; 652 653 654 655 static struct platform_suspend_ops omap_pm_ops ={ 656 .prepare = omap_pm_prepare, 657 .enter = omap_pm_enter, 658 .finish = omap_pm_finish, 659 .valid = suspend_valid_only_mem, 660 }; 661 662 static int __init omap_pm_init(void) 663 { 664 665 #ifdef CONFIG_OMAP_32K_TIMER 666 int error; 667 #endif 668 669 printk("Power Management for TI OMAP.\n"); 670 671 /* 672 * We copy the assembler sleep/wakeup routines to SRAM. 673 * These routines need to be in SRAM as that's the only 674 * memory the MPU can see when it wakes up. 675 */ 676 if (cpu_is_omap730()) { 677 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, 678 omap730_cpu_suspend_sz); 679 } else if (cpu_is_omap15xx()) { 680 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 681 omap1510_cpu_suspend_sz); 682 } else if (cpu_is_omap16xx()) { 683 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, 684 omap1610_cpu_suspend_sz); 685 } 686 687 if (omap_sram_suspend == NULL) { 688 printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); 689 return -ENODEV; 690 } 691 692 pm_idle = omap_pm_idle; 693 694 if (cpu_is_omap730()) 695 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); 696 else if (cpu_is_omap16xx()) 697 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); 698 699 /* Program new power ramp-up time 700 * (0 for most boards since we don't lower voltage when in deep sleep) 701 */ 702 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); 703 704 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ 705 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); 706 707 /* Configure IDLECT3 */ 708 if (cpu_is_omap730()) 709 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3); 710 else if (cpu_is_omap16xx()) 711 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); 712 713 suspend_set_ops(&omap_pm_ops); 714 715 #if defined(DEBUG) && defined(CONFIG_PROC_FS) 716 omap_pm_init_proc(); 717 #endif 718 719 #ifdef CONFIG_OMAP_32K_TIMER 720 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); 721 if (error) 722 printk(KERN_ERR "sysfs_create_file failed: %d\n", error); 723 #endif 724 725 if (cpu_is_omap16xx()) { 726 /* configure LOW_PWR pin */ 727 omap_cfg_reg(T20_1610_LOW_PWR); 728 } 729 730 return 0; 731 } 732 __initcall(omap_pm_init); 733