1 /* 2 * linux/arch/arm/mach-omap1/irq.c 3 * 4 * Interrupt handler for all OMAP boards 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com> 9 * 10 * Completely re-written to support various OMAP chips with bank specific 11 * interrupt handlers. 12 * 13 * Some snippets of the code taken from the older OMAP interrupt handler 14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 #include <linux/gpio.h> 39 #include <linux/init.h> 40 #include <linux/module.h> 41 #include <linux/sched.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 45 #include <asm/irq.h> 46 #include <asm/mach/irq.h> 47 48 #include "soc.h" 49 50 #include <mach/hardware.h> 51 52 #include "common.h" 53 54 #define IRQ_BANK(irq) ((irq) >> 5) 55 #define IRQ_BIT(irq) ((irq) & 0x1f) 56 57 struct omap_irq_bank { 58 unsigned long base_reg; 59 unsigned long trigger_map; 60 unsigned long wake_enable; 61 }; 62 63 u32 omap_irq_flags; 64 static unsigned int irq_bank_count; 65 static struct omap_irq_bank *irq_banks; 66 67 static inline unsigned int irq_bank_readl(int bank, int offset) 68 { 69 return omap_readl(irq_banks[bank].base_reg + offset); 70 } 71 72 static inline void irq_bank_writel(unsigned long value, int bank, int offset) 73 { 74 omap_writel(value, irq_banks[bank].base_reg + offset); 75 } 76 77 static void omap_ack_irq(struct irq_data *d) 78 { 79 if (d->irq > 31) 80 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); 81 82 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); 83 } 84 85 static void omap_mask_irq(struct irq_data *d) 86 { 87 int bank = IRQ_BANK(d->irq); 88 u32 l; 89 90 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 91 l |= 1 << IRQ_BIT(d->irq); 92 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 93 } 94 95 static void omap_unmask_irq(struct irq_data *d) 96 { 97 int bank = IRQ_BANK(d->irq); 98 u32 l; 99 100 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 101 l &= ~(1 << IRQ_BIT(d->irq)); 102 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 103 } 104 105 static void omap_mask_ack_irq(struct irq_data *d) 106 { 107 omap_mask_irq(d); 108 omap_ack_irq(d); 109 } 110 111 static int omap_wake_irq(struct irq_data *d, unsigned int enable) 112 { 113 int bank = IRQ_BANK(d->irq); 114 115 if (enable) 116 irq_banks[bank].wake_enable |= IRQ_BIT(d->irq); 117 else 118 irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq); 119 120 return 0; 121 } 122 123 124 /* 125 * Allows tuning the IRQ type and priority 126 * 127 * NOTE: There is currently no OMAP fiq handler for Linux. Read the 128 * mailing list threads on FIQ handlers if you are planning to 129 * add a FIQ handler for OMAP. 130 */ 131 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 132 { 133 signed int bank; 134 unsigned long val, offset; 135 136 bank = IRQ_BANK(irq); 137 /* FIQ is only available on bank 0 interrupts */ 138 fiq = bank ? 0 : (fiq & 0x1); 139 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); 140 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; 141 irq_bank_writel(val, bank, offset); 142 } 143 144 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) 145 static struct omap_irq_bank omap7xx_irq_banks[] = { 146 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, 147 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, 148 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, 149 }; 150 #endif 151 152 #ifdef CONFIG_ARCH_OMAP15XX 153 static struct omap_irq_bank omap1510_irq_banks[] = { 154 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 155 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 156 }; 157 static struct omap_irq_bank omap310_irq_banks[] = { 158 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, 159 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, 160 }; 161 #endif 162 163 #if defined(CONFIG_ARCH_OMAP16XX) 164 165 static struct omap_irq_bank omap1610_irq_banks[] = { 166 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 167 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 168 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 169 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 170 }; 171 #endif 172 173 static struct irq_chip omap_irq_chip = { 174 .name = "MPU", 175 .irq_ack = omap_mask_ack_irq, 176 .irq_mask = omap_mask_irq, 177 .irq_unmask = omap_unmask_irq, 178 .irq_set_wake = omap_wake_irq, 179 }; 180 181 void __init omap1_init_irq(void) 182 { 183 int i, j; 184 185 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 186 if (cpu_is_omap7xx()) { 187 omap_irq_flags = INT_7XX_IH2_IRQ; 188 irq_banks = omap7xx_irq_banks; 189 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); 190 } 191 #endif 192 #ifdef CONFIG_ARCH_OMAP15XX 193 if (cpu_is_omap1510()) { 194 omap_irq_flags = INT_1510_IH2_IRQ; 195 irq_banks = omap1510_irq_banks; 196 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 197 } 198 if (cpu_is_omap310()) { 199 omap_irq_flags = INT_1510_IH2_IRQ; 200 irq_banks = omap310_irq_banks; 201 irq_bank_count = ARRAY_SIZE(omap310_irq_banks); 202 } 203 #endif 204 #if defined(CONFIG_ARCH_OMAP16XX) 205 if (cpu_is_omap16xx()) { 206 omap_irq_flags = INT_1510_IH2_IRQ; 207 irq_banks = omap1610_irq_banks; 208 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); 209 } 210 #endif 211 printk("Total of %i interrupts in %i interrupt banks\n", 212 irq_bank_count * 32, irq_bank_count); 213 214 /* Mask and clear all interrupts */ 215 for (i = 0; i < irq_bank_count; i++) { 216 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); 217 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); 218 } 219 220 /* Clear any pending interrupts */ 221 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); 222 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); 223 224 /* Enable interrupts in global mask */ 225 if (cpu_is_omap7xx()) 226 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); 227 228 /* Install the interrupt handlers for each bank */ 229 for (i = 0; i < irq_bank_count; i++) { 230 for (j = i * 32; j < (i + 1) * 32; j++) { 231 int irq_trigger; 232 233 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 234 omap_irq_set_cfg(j, 0, 0, irq_trigger); 235 236 irq_set_chip_and_handler(j, &omap_irq_chip, 237 handle_level_irq); 238 set_irq_flags(j, IRQF_VALID); 239 } 240 } 241 242 /* Unmask level 2 handler */ 243 244 if (cpu_is_omap7xx()) 245 omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ)); 246 else if (cpu_is_omap15xx()) 247 omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ)); 248 else if (cpu_is_omap16xx()) 249 omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ)); 250 } 251