1 /* 2 * linux/arch/arm/mach-omap1/irq.c 3 * 4 * Interrupt handler for all OMAP boards 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com> 9 * 10 * Completely re-written to support various OMAP chips with bank specific 11 * interrupt handlers. 12 * 13 * Some snippets of the code taken from the older OMAP interrupt handler 14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 #include <linux/gpio.h> 39 #include <linux/init.h> 40 #include <linux/module.h> 41 #include <linux/sched.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 45 #include <asm/irq.h> 46 #include <asm/exception.h> 47 #include <asm/mach/irq.h> 48 49 #include "soc.h" 50 #include "hardware.h" 51 #include "common.h" 52 53 #define IRQ_BANK(irq) ((irq) >> 5) 54 #define IRQ_BIT(irq) ((irq) & 0x1f) 55 56 struct omap_irq_bank { 57 unsigned long base_reg; 58 void __iomem *va; 59 unsigned long trigger_map; 60 unsigned long wake_enable; 61 }; 62 63 static u32 omap_l2_irq; 64 static unsigned int irq_bank_count; 65 static struct omap_irq_bank *irq_banks; 66 static struct irq_domain *domain; 67 68 static inline unsigned int irq_bank_readl(int bank, int offset) 69 { 70 return readl_relaxed(irq_banks[bank].va + offset); 71 } 72 static inline void irq_bank_writel(unsigned long value, int bank, int offset) 73 { 74 writel_relaxed(value, irq_banks[bank].va + offset); 75 } 76 77 static void omap_ack_irq(int irq) 78 { 79 if (irq > 31) 80 writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET); 81 82 writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET); 83 } 84 85 static void omap_mask_ack_irq(struct irq_data *d) 86 { 87 struct irq_chip_type *ct = irq_data_get_chip_type(d); 88 89 ct->chip.irq_mask(d); 90 omap_ack_irq(d->irq); 91 } 92 93 /* 94 * Allows tuning the IRQ type and priority 95 * 96 * NOTE: There is currently no OMAP fiq handler for Linux. Read the 97 * mailing list threads on FIQ handlers if you are planning to 98 * add a FIQ handler for OMAP. 99 */ 100 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 101 { 102 signed int bank; 103 unsigned long val, offset; 104 105 bank = IRQ_BANK(irq); 106 /* FIQ is only available on bank 0 interrupts */ 107 fiq = bank ? 0 : (fiq & 0x1); 108 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); 109 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; 110 irq_bank_writel(val, bank, offset); 111 } 112 113 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) 114 static struct omap_irq_bank omap7xx_irq_banks[] = { 115 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, 116 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, 117 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, 118 }; 119 #endif 120 121 #ifdef CONFIG_ARCH_OMAP15XX 122 static struct omap_irq_bank omap1510_irq_banks[] = { 123 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 124 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 125 }; 126 static struct omap_irq_bank omap310_irq_banks[] = { 127 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, 128 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, 129 }; 130 #endif 131 132 #if defined(CONFIG_ARCH_OMAP16XX) 133 134 static struct omap_irq_bank omap1610_irq_banks[] = { 135 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 136 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 137 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 138 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 139 }; 140 #endif 141 142 asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs) 143 { 144 void __iomem *l1 = irq_banks[0].va; 145 void __iomem *l2 = irq_banks[1].va; 146 u32 irqnr; 147 148 do { 149 irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); 150 irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); 151 if (!irqnr) 152 break; 153 154 irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); 155 if (irqnr) 156 goto irq; 157 158 irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); 159 if (irqnr == omap_l2_irq) { 160 irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); 161 if (irqnr) 162 irqnr += 32; 163 } 164 irq: 165 if (irqnr) 166 generic_handle_domain_irq(domain, irqnr); 167 else 168 break; 169 } while (irqnr); 170 } 171 172 static __init void 173 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 174 { 175 struct irq_chip_generic *gc; 176 struct irq_chip_type *ct; 177 178 gc = irq_alloc_generic_chip("MPU", 1, irq_start, base, 179 handle_level_irq); 180 ct = gc->chip_types; 181 ct->chip.irq_ack = omap_mask_ack_irq; 182 ct->chip.irq_mask = irq_gc_mask_set_bit; 183 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 184 ct->chip.irq_set_wake = irq_gc_set_wake; 185 ct->regs.mask = IRQ_MIR_REG_OFFSET; 186 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 187 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 188 } 189 190 void __init omap1_init_irq(void) 191 { 192 struct irq_chip_type *ct; 193 struct irq_data *d = NULL; 194 int i, j, irq_base; 195 unsigned long nr_irqs; 196 197 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 198 if (cpu_is_omap7xx()) { 199 irq_banks = omap7xx_irq_banks; 200 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); 201 } 202 #endif 203 #ifdef CONFIG_ARCH_OMAP15XX 204 if (cpu_is_omap1510()) { 205 irq_banks = omap1510_irq_banks; 206 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 207 } 208 if (cpu_is_omap310()) { 209 irq_banks = omap310_irq_banks; 210 irq_bank_count = ARRAY_SIZE(omap310_irq_banks); 211 } 212 #endif 213 #if defined(CONFIG_ARCH_OMAP16XX) 214 if (cpu_is_omap16xx()) { 215 irq_banks = omap1610_irq_banks; 216 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); 217 } 218 #endif 219 220 for (i = 0; i < irq_bank_count; i++) { 221 irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); 222 if (WARN_ON(!irq_banks[i].va)) 223 return; 224 } 225 226 nr_irqs = irq_bank_count * 32; 227 228 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); 229 if (irq_base < 0) { 230 pr_warn("Couldn't allocate IRQ numbers\n"); 231 irq_base = 0; 232 } 233 omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base; 234 omap_l2_irq -= NR_IRQS_LEGACY; 235 236 domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, 237 &irq_domain_simple_ops, NULL); 238 239 pr_info("Total of %lu interrupts in %i interrupt banks\n", 240 nr_irqs, irq_bank_count); 241 242 /* Mask and clear all interrupts */ 243 for (i = 0; i < irq_bank_count; i++) { 244 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); 245 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); 246 } 247 248 /* Clear any pending interrupts */ 249 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); 250 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); 251 252 /* Enable interrupts in global mask */ 253 if (cpu_is_omap7xx()) 254 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); 255 256 /* Install the interrupt handlers for each bank */ 257 for (i = 0; i < irq_bank_count; i++) { 258 for (j = i * 32; j < (i + 1) * 32; j++) { 259 int irq_trigger; 260 261 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 262 omap_irq_set_cfg(j, 0, 0, irq_trigger); 263 irq_clear_status_flags(j, IRQ_NOREQUEST); 264 } 265 omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); 266 } 267 268 /* Unmask level 2 handler */ 269 d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq)); 270 if (d) { 271 ct = irq_data_get_chip_type(d); 272 ct->chip.irq_unmask(d); 273 } 274 } 275