1 /* 2 * linux/arch/arm/mach-omap1/irq.c 3 * 4 * Interrupt handler for all OMAP boards 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com> 9 * 10 * Completely re-written to support various OMAP chips with bank specific 11 * interrupt handlers. 12 * 13 * Some snippets of the code taken from the older OMAP interrupt handler 14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 #include <linux/gpio.h> 39 #include <linux/init.h> 40 #include <linux/irq.h> 41 #include <linux/module.h> 42 #include <linux/sched.h> 43 #include <linux/interrupt.h> 44 #include <linux/io.h> 45 #include <linux/irqdomain.h> 46 47 #include <asm/irq.h> 48 #include <asm/exception.h> 49 #include <asm/mach/irq.h> 50 51 #include "soc.h" 52 #include "hardware.h" 53 #include "common.h" 54 55 #define IRQ_BANK(irq) ((irq) >> 5) 56 #define IRQ_BIT(irq) ((irq) & 0x1f) 57 58 struct omap_irq_bank { 59 unsigned long base_reg; 60 void __iomem *va; 61 unsigned long trigger_map; 62 unsigned long wake_enable; 63 }; 64 65 static u32 omap_l2_irq; 66 static unsigned int irq_bank_count; 67 static struct omap_irq_bank *irq_banks; 68 static struct irq_domain *domain; 69 70 static inline unsigned int irq_bank_readl(int bank, int offset) 71 { 72 return readl_relaxed(irq_banks[bank].va + offset); 73 } 74 static inline void irq_bank_writel(unsigned long value, int bank, int offset) 75 { 76 writel_relaxed(value, irq_banks[bank].va + offset); 77 } 78 79 static void omap_ack_irq(int irq) 80 { 81 if (irq > 31) 82 writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET); 83 84 writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET); 85 } 86 87 static void omap_mask_ack_irq(struct irq_data *d) 88 { 89 struct irq_chip_type *ct = irq_data_get_chip_type(d); 90 91 ct->chip.irq_mask(d); 92 omap_ack_irq(d->irq); 93 } 94 95 /* 96 * Allows tuning the IRQ type and priority 97 * 98 * NOTE: There is currently no OMAP fiq handler for Linux. Read the 99 * mailing list threads on FIQ handlers if you are planning to 100 * add a FIQ handler for OMAP. 101 */ 102 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 103 { 104 signed int bank; 105 unsigned long val, offset; 106 107 bank = IRQ_BANK(irq); 108 /* FIQ is only available on bank 0 interrupts */ 109 fiq = bank ? 0 : (fiq & 0x1); 110 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); 111 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; 112 irq_bank_writel(val, bank, offset); 113 } 114 115 #ifdef CONFIG_ARCH_OMAP15XX 116 static struct omap_irq_bank omap1510_irq_banks[] = { 117 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 118 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 119 }; 120 static struct omap_irq_bank omap310_irq_banks[] = { 121 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, 122 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, 123 }; 124 #endif 125 126 #if defined(CONFIG_ARCH_OMAP16XX) 127 128 static struct omap_irq_bank omap1610_irq_banks[] = { 129 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 130 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 131 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 132 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 133 }; 134 #endif 135 136 asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs) 137 { 138 void __iomem *l1 = irq_banks[0].va; 139 void __iomem *l2 = irq_banks[1].va; 140 u32 irqnr; 141 142 do { 143 irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); 144 irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); 145 if (!irqnr) 146 break; 147 148 irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); 149 if (irqnr) 150 goto irq; 151 152 irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); 153 if (irqnr == omap_l2_irq) { 154 irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); 155 if (irqnr) 156 irqnr += 32; 157 } 158 irq: 159 if (irqnr) 160 generic_handle_domain_irq(domain, irqnr); 161 else 162 break; 163 } while (irqnr); 164 } 165 166 static __init void 167 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 168 { 169 struct irq_chip_generic *gc; 170 struct irq_chip_type *ct; 171 172 gc = irq_alloc_generic_chip("MPU", 1, irq_start, base, 173 handle_level_irq); 174 ct = gc->chip_types; 175 ct->chip.irq_ack = omap_mask_ack_irq; 176 ct->chip.irq_mask = irq_gc_mask_set_bit; 177 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 178 ct->chip.irq_set_wake = irq_gc_set_wake; 179 ct->regs.mask = IRQ_MIR_REG_OFFSET; 180 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 181 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 182 } 183 184 void __init omap1_init_irq(void) 185 { 186 struct irq_chip_type *ct; 187 struct irq_data *d = NULL; 188 int i, j, irq_base; 189 unsigned long nr_irqs; 190 191 #ifdef CONFIG_ARCH_OMAP15XX 192 if (cpu_is_omap1510()) { 193 irq_banks = omap1510_irq_banks; 194 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 195 } 196 if (cpu_is_omap310()) { 197 irq_banks = omap310_irq_banks; 198 irq_bank_count = ARRAY_SIZE(omap310_irq_banks); 199 } 200 #endif 201 #if defined(CONFIG_ARCH_OMAP16XX) 202 if (cpu_is_omap16xx()) { 203 irq_banks = omap1610_irq_banks; 204 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); 205 } 206 #endif 207 208 for (i = 0; i < irq_bank_count; i++) { 209 irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); 210 if (WARN_ON(!irq_banks[i].va)) 211 return; 212 } 213 214 nr_irqs = irq_bank_count * 32; 215 216 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); 217 if (irq_base < 0) { 218 pr_warn("Couldn't allocate IRQ numbers\n"); 219 irq_base = 0; 220 } 221 omap_l2_irq = irq_base; 222 omap_l2_irq -= NR_IRQS_LEGACY; 223 224 domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, 225 &irq_domain_simple_ops, NULL); 226 227 pr_info("Total of %lu interrupts in %i interrupt banks\n", 228 nr_irqs, irq_bank_count); 229 230 /* Mask and clear all interrupts */ 231 for (i = 0; i < irq_bank_count; i++) { 232 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); 233 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); 234 } 235 236 /* Clear any pending interrupts */ 237 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); 238 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); 239 240 /* Install the interrupt handlers for each bank */ 241 for (i = 0; i < irq_bank_count; i++) { 242 for (j = i * 32; j < (i + 1) * 32; j++) { 243 int irq_trigger; 244 245 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 246 omap_irq_set_cfg(j, 0, 0, irq_trigger); 247 irq_clear_status_flags(j, IRQ_NOREQUEST); 248 } 249 omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); 250 } 251 252 /* Unmask level 2 handler */ 253 d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq)); 254 if (d) { 255 ct = irq_data_get_chip_type(d); 256 ct->chip.irq_unmask(d); 257 } 258 259 set_handle_irq(omap1_handle_irq); 260 } 261