1 /* 2 * linux/arch/arm/mach-omap1/irq.c 3 * 4 * Interrupt handler for all OMAP boards 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com> 9 * 10 * Completely re-written to support various OMAP chips with bank specific 11 * interrupt handlers. 12 * 13 * Some snippets of the code taken from the older OMAP interrupt handler 14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 #include <linux/gpio.h> 39 #include <linux/init.h> 40 #include <linux/module.h> 41 #include <linux/sched.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 45 #include <asm/irq.h> 46 #include <asm/exception.h> 47 #include <asm/mach/irq.h> 48 49 #include "soc.h" 50 #include "hardware.h" 51 #include "common.h" 52 53 #define IRQ_BANK(irq) ((irq) >> 5) 54 #define IRQ_BIT(irq) ((irq) & 0x1f) 55 56 struct omap_irq_bank { 57 unsigned long base_reg; 58 void __iomem *va; 59 unsigned long trigger_map; 60 unsigned long wake_enable; 61 }; 62 63 static u32 omap_l2_irq; 64 static unsigned int irq_bank_count; 65 static struct omap_irq_bank *irq_banks; 66 static struct irq_domain *domain; 67 68 static inline unsigned int irq_bank_readl(int bank, int offset) 69 { 70 return readl_relaxed(irq_banks[bank].va + offset); 71 } 72 static inline void irq_bank_writel(unsigned long value, int bank, int offset) 73 { 74 writel_relaxed(value, irq_banks[bank].va + offset); 75 } 76 77 static void omap_ack_irq(int irq) 78 { 79 if (irq > 31) 80 writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET); 81 82 writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET); 83 } 84 85 static void omap_mask_ack_irq(struct irq_data *d) 86 { 87 struct irq_chip_type *ct = irq_data_get_chip_type(d); 88 89 ct->chip.irq_mask(d); 90 omap_ack_irq(d->irq); 91 } 92 93 /* 94 * Allows tuning the IRQ type and priority 95 * 96 * NOTE: There is currently no OMAP fiq handler for Linux. Read the 97 * mailing list threads on FIQ handlers if you are planning to 98 * add a FIQ handler for OMAP. 99 */ 100 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 101 { 102 signed int bank; 103 unsigned long val, offset; 104 105 bank = IRQ_BANK(irq); 106 /* FIQ is only available on bank 0 interrupts */ 107 fiq = bank ? 0 : (fiq & 0x1); 108 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); 109 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; 110 irq_bank_writel(val, bank, offset); 111 } 112 113 #ifdef CONFIG_ARCH_OMAP15XX 114 static struct omap_irq_bank omap1510_irq_banks[] = { 115 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 116 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 117 }; 118 static struct omap_irq_bank omap310_irq_banks[] = { 119 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, 120 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, 121 }; 122 #endif 123 124 #if defined(CONFIG_ARCH_OMAP16XX) 125 126 static struct omap_irq_bank omap1610_irq_banks[] = { 127 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 128 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 129 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 130 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 131 }; 132 #endif 133 134 asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs) 135 { 136 void __iomem *l1 = irq_banks[0].va; 137 void __iomem *l2 = irq_banks[1].va; 138 u32 irqnr; 139 140 do { 141 irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); 142 irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); 143 if (!irqnr) 144 break; 145 146 irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); 147 if (irqnr) 148 goto irq; 149 150 irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); 151 if (irqnr == omap_l2_irq) { 152 irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); 153 if (irqnr) 154 irqnr += 32; 155 } 156 irq: 157 if (irqnr) 158 generic_handle_domain_irq(domain, irqnr); 159 else 160 break; 161 } while (irqnr); 162 } 163 164 static __init void 165 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 166 { 167 struct irq_chip_generic *gc; 168 struct irq_chip_type *ct; 169 170 gc = irq_alloc_generic_chip("MPU", 1, irq_start, base, 171 handle_level_irq); 172 ct = gc->chip_types; 173 ct->chip.irq_ack = omap_mask_ack_irq; 174 ct->chip.irq_mask = irq_gc_mask_set_bit; 175 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 176 ct->chip.irq_set_wake = irq_gc_set_wake; 177 ct->regs.mask = IRQ_MIR_REG_OFFSET; 178 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 179 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 180 } 181 182 void __init omap1_init_irq(void) 183 { 184 struct irq_chip_type *ct; 185 struct irq_data *d = NULL; 186 int i, j, irq_base; 187 unsigned long nr_irqs; 188 189 #ifdef CONFIG_ARCH_OMAP15XX 190 if (cpu_is_omap1510()) { 191 irq_banks = omap1510_irq_banks; 192 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 193 } 194 if (cpu_is_omap310()) { 195 irq_banks = omap310_irq_banks; 196 irq_bank_count = ARRAY_SIZE(omap310_irq_banks); 197 } 198 #endif 199 #if defined(CONFIG_ARCH_OMAP16XX) 200 if (cpu_is_omap16xx()) { 201 irq_banks = omap1610_irq_banks; 202 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); 203 } 204 #endif 205 206 for (i = 0; i < irq_bank_count; i++) { 207 irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); 208 if (WARN_ON(!irq_banks[i].va)) 209 return; 210 } 211 212 nr_irqs = irq_bank_count * 32; 213 214 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); 215 if (irq_base < 0) { 216 pr_warn("Couldn't allocate IRQ numbers\n"); 217 irq_base = 0; 218 } 219 omap_l2_irq = irq_base; 220 omap_l2_irq -= NR_IRQS_LEGACY; 221 222 domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, 223 &irq_domain_simple_ops, NULL); 224 225 pr_info("Total of %lu interrupts in %i interrupt banks\n", 226 nr_irqs, irq_bank_count); 227 228 /* Mask and clear all interrupts */ 229 for (i = 0; i < irq_bank_count; i++) { 230 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); 231 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); 232 } 233 234 /* Clear any pending interrupts */ 235 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); 236 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); 237 238 /* Install the interrupt handlers for each bank */ 239 for (i = 0; i < irq_bank_count; i++) { 240 for (j = i * 32; j < (i + 1) * 32; j++) { 241 int irq_trigger; 242 243 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 244 omap_irq_set_cfg(j, 0, 0, irq_trigger); 245 irq_clear_status_flags(j, IRQ_NOREQUEST); 246 } 247 omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); 248 } 249 250 /* Unmask level 2 handler */ 251 d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq)); 252 if (d) { 253 ct = irq_data_get_chip_type(d); 254 ct->chip.irq_unmask(d); 255 } 256 } 257