1 /* 2 * OMAP1/OMAP7xx - specific DMA driver 3 * 4 * Copyright (C) 2003 - 2008 Nokia Corporation 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 7 * Graphics DMA and LCD DMA graphics tranformations 8 * by Imre Deak <imre.deak@nokia.com> 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. 10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * 12 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 13 * Converted DMA library into platform driver 14 * - G, Manjunath Kondaiah <manjugk@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #include <linux/err.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/init.h> 25 #include <linux/device.h> 26 #include <linux/io.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/omap-dma.h> 29 #include <mach/tc.h> 30 31 #include <mach/irqs.h> 32 33 #define OMAP1_DMA_BASE (0xfffed800) 34 #define OMAP1_LOGICAL_DMA_CH_COUNT 17 35 #define OMAP1_DMA_STRIDE 0x40 36 37 static u32 errata; 38 static u32 enable_1510_mode; 39 static u8 dma_stride; 40 static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; 41 42 static u16 reg_map[] = { 43 [GCR] = 0x400, 44 [GSCR] = 0x404, 45 [GRST1] = 0x408, 46 [HW_ID] = 0x442, 47 [PCH2_ID] = 0x444, 48 [PCH0_ID] = 0x446, 49 [PCH1_ID] = 0x448, 50 [PCHG_ID] = 0x44a, 51 [PCHD_ID] = 0x44c, 52 [CAPS_0] = 0x44e, 53 [CAPS_1] = 0x452, 54 [CAPS_2] = 0x456, 55 [CAPS_3] = 0x458, 56 [CAPS_4] = 0x45a, 57 [PCH2_SR] = 0x460, 58 [PCH0_SR] = 0x480, 59 [PCH1_SR] = 0x482, 60 [PCHD_SR] = 0x4c0, 61 62 /* Common Registers */ 63 [CSDP] = 0x00, 64 [CCR] = 0x02, 65 [CICR] = 0x04, 66 [CSR] = 0x06, 67 [CEN] = 0x10, 68 [CFN] = 0x12, 69 [CSFI] = 0x14, 70 [CSEI] = 0x16, 71 [CPC] = 0x18, /* 15xx only */ 72 [CSAC] = 0x18, 73 [CDAC] = 0x1a, 74 [CDEI] = 0x1c, 75 [CDFI] = 0x1e, 76 [CLNK_CTRL] = 0x28, 77 78 /* Channel specific register offsets */ 79 [CSSA] = 0x08, 80 [CDSA] = 0x0c, 81 [COLOR] = 0x20, 82 [CCR2] = 0x24, 83 [LCH_CTRL] = 0x2a, 84 }; 85 86 static struct resource res[] __initdata = { 87 [0] = { 88 .start = OMAP1_DMA_BASE, 89 .end = OMAP1_DMA_BASE + SZ_2K - 1, 90 .flags = IORESOURCE_MEM, 91 }, 92 [1] = { 93 .name = "0", 94 .start = INT_DMA_CH0_6, 95 .flags = IORESOURCE_IRQ, 96 }, 97 [2] = { 98 .name = "1", 99 .start = INT_DMA_CH1_7, 100 .flags = IORESOURCE_IRQ, 101 }, 102 [3] = { 103 .name = "2", 104 .start = INT_DMA_CH2_8, 105 .flags = IORESOURCE_IRQ, 106 }, 107 [4] = { 108 .name = "3", 109 .start = INT_DMA_CH3, 110 .flags = IORESOURCE_IRQ, 111 }, 112 [5] = { 113 .name = "4", 114 .start = INT_DMA_CH4, 115 .flags = IORESOURCE_IRQ, 116 }, 117 [6] = { 118 .name = "5", 119 .start = INT_DMA_CH5, 120 .flags = IORESOURCE_IRQ, 121 }, 122 /* Handled in lcd_dma.c */ 123 [7] = { 124 .name = "6", 125 .start = INT_1610_DMA_CH6, 126 .flags = IORESOURCE_IRQ, 127 }, 128 /* irq's for omap16xx and omap7xx */ 129 [8] = { 130 .name = "7", 131 .start = INT_1610_DMA_CH7, 132 .flags = IORESOURCE_IRQ, 133 }, 134 [9] = { 135 .name = "8", 136 .start = INT_1610_DMA_CH8, 137 .flags = IORESOURCE_IRQ, 138 }, 139 [10] = { 140 .name = "9", 141 .start = INT_1610_DMA_CH9, 142 .flags = IORESOURCE_IRQ, 143 }, 144 [11] = { 145 .name = "10", 146 .start = INT_1610_DMA_CH10, 147 .flags = IORESOURCE_IRQ, 148 }, 149 [12] = { 150 .name = "11", 151 .start = INT_1610_DMA_CH11, 152 .flags = IORESOURCE_IRQ, 153 }, 154 [13] = { 155 .name = "12", 156 .start = INT_1610_DMA_CH12, 157 .flags = IORESOURCE_IRQ, 158 }, 159 [14] = { 160 .name = "13", 161 .start = INT_1610_DMA_CH13, 162 .flags = IORESOURCE_IRQ, 163 }, 164 [15] = { 165 .name = "14", 166 .start = INT_1610_DMA_CH14, 167 .flags = IORESOURCE_IRQ, 168 }, 169 [16] = { 170 .name = "15", 171 .start = INT_1610_DMA_CH15, 172 .flags = IORESOURCE_IRQ, 173 }, 174 [17] = { 175 .name = "16", 176 .start = INT_DMA_LCD, 177 .flags = IORESOURCE_IRQ, 178 }, 179 }; 180 181 static void __iomem *dma_base; 182 static inline void dma_write(u32 val, int reg, int lch) 183 { 184 u8 stride; 185 u32 offset; 186 187 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 188 offset = reg_map[reg] + (stride * lch); 189 190 __raw_writew(val, dma_base + offset); 191 if ((reg > CLNK_CTRL && reg < CCEN) || 192 (reg > PCHD_ID && reg < CAPS_2)) { 193 u32 offset2 = reg_map[reg] + 2 + (stride * lch); 194 __raw_writew(val >> 16, dma_base + offset2); 195 } 196 } 197 198 static inline u32 dma_read(int reg, int lch) 199 { 200 u8 stride; 201 u32 offset, val; 202 203 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 204 offset = reg_map[reg] + (stride * lch); 205 206 val = __raw_readw(dma_base + offset); 207 if ((reg > CLNK_CTRL && reg < CCEN) || 208 (reg > PCHD_ID && reg < CAPS_2)) { 209 u16 upper; 210 u32 offset2 = reg_map[reg] + 2 + (stride * lch); 211 upper = __raw_readw(dma_base + offset2); 212 val |= (upper << 16); 213 } 214 return val; 215 } 216 217 static void omap1_clear_lch_regs(int lch) 218 { 219 int i = dma_common_ch_start; 220 221 for (; i <= dma_common_ch_end; i += 1) 222 dma_write(0, i, lch); 223 } 224 225 static void omap1_clear_dma(int lch) 226 { 227 u32 l; 228 229 l = dma_read(CCR, lch); 230 l &= ~OMAP_DMA_CCR_EN; 231 dma_write(l, CCR, lch); 232 233 /* Clear pending interrupts */ 234 l = dma_read(CSR, lch); 235 } 236 237 static void omap1_show_dma_caps(void) 238 { 239 if (enable_1510_mode) { 240 printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); 241 } else { 242 u16 w; 243 printk(KERN_INFO "OMAP DMA hardware version %d\n", 244 dma_read(HW_ID, 0)); 245 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", 246 dma_read(CAPS_0, 0), dma_read(CAPS_1, 0), 247 dma_read(CAPS_2, 0), dma_read(CAPS_3, 0), 248 dma_read(CAPS_4, 0)); 249 250 /* Disable OMAP 3.0/3.1 compatibility mode. */ 251 w = dma_read(GSCR, 0); 252 w |= 1 << 3; 253 dma_write(w, GSCR, 0); 254 } 255 return; 256 } 257 258 static u32 configure_dma_errata(void) 259 { 260 261 /* 262 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is 263 * read before the DMA controller finished disabling the channel. 264 */ 265 if (!cpu_is_omap15xx()) 266 SET_DMA_ERRATA(DMA_ERRATA_3_3); 267 268 return errata; 269 } 270 271 static const struct platform_device_info omap_dma_dev_info = { 272 .name = "omap-dma-engine", 273 .id = -1, 274 .dma_mask = DMA_BIT_MASK(32), 275 }; 276 277 static int __init omap1_system_dma_init(void) 278 { 279 struct omap_system_dma_plat_info *p; 280 struct omap_dma_dev_attr *d; 281 struct platform_device *pdev, *dma_pdev; 282 int ret; 283 284 pdev = platform_device_alloc("omap_dma_system", 0); 285 if (!pdev) { 286 pr_err("%s: Unable to device alloc for dma\n", 287 __func__); 288 return -ENOMEM; 289 } 290 291 dma_base = ioremap(res[0].start, resource_size(&res[0])); 292 if (!dma_base) { 293 pr_err("%s: Unable to ioremap\n", __func__); 294 ret = -ENODEV; 295 goto exit_device_put; 296 } 297 298 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); 299 if (ret) { 300 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", 301 __func__, pdev->name, pdev->id); 302 goto exit_iounmap; 303 } 304 305 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); 306 if (!p) { 307 dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n", 308 __func__, pdev->name); 309 ret = -ENOMEM; 310 goto exit_iounmap; 311 } 312 313 d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL); 314 if (!d) { 315 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n", 316 __func__, pdev->name); 317 ret = -ENOMEM; 318 goto exit_release_p; 319 } 320 321 d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; 322 323 /* Valid attributes for omap1 plus processors */ 324 if (cpu_is_omap15xx()) 325 d->dev_caps = ENABLE_1510_MODE; 326 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; 327 328 if (cpu_is_omap16xx()) 329 d->dev_caps = ENABLE_16XX_MODE; 330 331 d->dev_caps |= SRC_PORT; 332 d->dev_caps |= DST_PORT; 333 d->dev_caps |= SRC_INDEX; 334 d->dev_caps |= DST_INDEX; 335 d->dev_caps |= IS_BURST_ONLY4; 336 d->dev_caps |= CLEAR_CSR_ON_READ; 337 d->dev_caps |= IS_WORD_16; 338 339 340 d->chan = kzalloc(sizeof(struct omap_dma_lch) * 341 (d->lch_count), GFP_KERNEL); 342 if (!d->chan) { 343 dev_err(&pdev->dev, 344 "%s: Memory allocation failed for d->chan!\n", 345 __func__); 346 ret = -ENOMEM; 347 goto exit_release_d; 348 } 349 350 if (cpu_is_omap15xx()) 351 d->chan_count = 9; 352 else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { 353 if (!(d->dev_caps & ENABLE_1510_MODE)) 354 d->chan_count = 16; 355 else 356 d->chan_count = 9; 357 } 358 359 p->dma_attr = d; 360 361 p->show_dma_caps = omap1_show_dma_caps; 362 p->clear_lch_regs = omap1_clear_lch_regs; 363 p->clear_dma = omap1_clear_dma; 364 p->dma_write = dma_write; 365 p->dma_read = dma_read; 366 p->disable_irq_lch = NULL; 367 368 p->errata = configure_dma_errata(); 369 370 ret = platform_device_add_data(pdev, p, sizeof(*p)); 371 if (ret) { 372 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", 373 __func__, pdev->name, pdev->id); 374 goto exit_release_chan; 375 } 376 377 ret = platform_device_add(pdev); 378 if (ret) { 379 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", 380 __func__, pdev->name, pdev->id); 381 goto exit_release_chan; 382 } 383 384 dma_stride = OMAP1_DMA_STRIDE; 385 dma_common_ch_start = CPC; 386 dma_common_ch_end = COLOR; 387 388 dma_pdev = platform_device_register_full(&omap_dma_dev_info); 389 if (IS_ERR(dma_pdev)) { 390 ret = PTR_ERR(dma_pdev); 391 goto exit_release_pdev; 392 } 393 394 return ret; 395 396 exit_release_pdev: 397 platform_device_del(pdev); 398 exit_release_chan: 399 kfree(d->chan); 400 exit_release_d: 401 kfree(d); 402 exit_release_p: 403 kfree(p); 404 exit_iounmap: 405 iounmap(dma_base); 406 exit_device_put: 407 platform_device_put(pdev); 408 409 return ret; 410 } 411 arch_initcall(omap1_system_dma_init); 412