1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-omap1/clock_data.c 4 * 5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation 6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 8 * 9 * To do: 10 * - Clocks that are only available on some chips should be marked with the 11 * chips that they are present on. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/io.h> 16 #include <linux/clk.h> 17 #include <linux/cpufreq.h> 18 #include <linux/delay.h> 19 #include <linux/soc/ti/omap1-io.h> 20 21 #include <asm/mach-types.h> /* for machine_is_* */ 22 23 #include "soc.h" 24 #include "hardware.h" 25 #include "usb.h" /* for OTG_BASE */ 26 #include "iomap.h" 27 #include "clock.h" 28 #include "sram.h" 29 30 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ 31 #define IDL_CLKOUT_ARM_SHIFT 12 32 #define IDLTIM_ARM_SHIFT 9 33 #define IDLAPI_ARM_SHIFT 8 34 #define IDLIF_ARM_SHIFT 6 35 #define IDLLB_ARM_SHIFT 4 /* undocumented? */ 36 #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ 37 #define IDLPER_ARM_SHIFT 2 38 #define IDLXORP_ARM_SHIFT 1 39 #define IDLWDT_ARM_SHIFT 0 40 41 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ 42 #define CONF_MOD_UART3_CLK_MODE_R 31 43 #define CONF_MOD_UART2_CLK_MODE_R 30 44 #define CONF_MOD_UART1_CLK_MODE_R 29 45 #define CONF_MOD_MMC_SD_CLK_REQ_R 23 46 #define CONF_MOD_MCBSP3_AUXON 20 47 48 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ 49 #define CONF_MOD_SOSSI_CLK_EN_R 16 50 51 /* Some OTG_SYSCON_2-specific bit fields */ 52 #define OTG_SYSCON_2_UHOST_EN_SHIFT 8 53 54 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ 55 #define SOFT_MMC2_DPLL_REQ_SHIFT 13 56 #define SOFT_MMC_DPLL_REQ_SHIFT 12 57 #define SOFT_UART3_DPLL_REQ_SHIFT 11 58 #define SOFT_UART2_DPLL_REQ_SHIFT 10 59 #define SOFT_UART1_DPLL_REQ_SHIFT 9 60 #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 61 #define SOFT_CAM_DPLL_REQ_SHIFT 7 62 #define SOFT_COM_MCKO_REQ_SHIFT 6 63 #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ 64 #define USB_REQ_EN_SHIFT 4 65 #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ 66 #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ 67 #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ 68 #define SOFT_DPLL_REQ_SHIFT 0 69 70 /* 71 * Omap1 clocks 72 */ 73 74 static struct clk ck_ref = { 75 .name = "ck_ref", 76 .ops = &clkops_null, 77 .rate = 12000000, 78 }; 79 80 static struct clk ck_dpll1 = { 81 .name = "ck_dpll1", 82 .ops = &clkops_null, 83 .parent = &ck_ref, 84 }; 85 86 /* 87 * FIXME: This clock seems to be necessary but no-one has asked for its 88 * activation. [ FIX: SoSSI, SSR ] 89 */ 90 static struct arm_idlect1_clk ck_dpll1out = { 91 .clk = { 92 .name = "ck_dpll1out", 93 .ops = &clkops_generic, 94 .parent = &ck_dpll1, 95 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, 96 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 97 .enable_bit = EN_CKOUT_ARM, 98 .recalc = &followparent_recalc, 99 }, 100 .idlect_shift = IDL_CLKOUT_ARM_SHIFT, 101 }; 102 103 static struct clk sossi_ck = { 104 .name = "ck_sossi", 105 .ops = &clkops_generic, 106 .parent = &ck_dpll1out.clk, 107 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, 108 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), 109 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, 110 .recalc = &omap1_sossi_recalc, 111 .set_rate = &omap1_set_sossi_rate, 112 }; 113 114 static struct clk arm_ck = { 115 .name = "arm_ck", 116 .ops = &clkops_null, 117 .parent = &ck_dpll1, 118 .rate_offset = CKCTL_ARMDIV_OFFSET, 119 .recalc = &omap1_ckctl_recalc, 120 .round_rate = omap1_clk_round_rate_ckctl_arm, 121 .set_rate = omap1_clk_set_rate_ckctl_arm, 122 }; 123 124 static struct arm_idlect1_clk armper_ck = { 125 .clk = { 126 .name = "armper_ck", 127 .ops = &clkops_generic, 128 .parent = &ck_dpll1, 129 .flags = CLOCK_IDLE_CONTROL, 130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 131 .enable_bit = EN_PERCK, 132 .rate_offset = CKCTL_PERDIV_OFFSET, 133 .recalc = &omap1_ckctl_recalc, 134 .round_rate = omap1_clk_round_rate_ckctl_arm, 135 .set_rate = omap1_clk_set_rate_ckctl_arm, 136 }, 137 .idlect_shift = IDLPER_ARM_SHIFT, 138 }; 139 140 /* 141 * FIXME: This clock seems to be necessary but no-one has asked for its 142 * activation. [ GPIO code for 1510 ] 143 */ 144 static struct clk arm_gpio_ck = { 145 .name = "ick", 146 .ops = &clkops_generic, 147 .parent = &ck_dpll1, 148 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 149 .enable_bit = EN_GPIOCK, 150 .recalc = &followparent_recalc, 151 }; 152 153 static struct arm_idlect1_clk armxor_ck = { 154 .clk = { 155 .name = "armxor_ck", 156 .ops = &clkops_generic, 157 .parent = &ck_ref, 158 .flags = CLOCK_IDLE_CONTROL, 159 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 160 .enable_bit = EN_XORPCK, 161 .recalc = &followparent_recalc, 162 }, 163 .idlect_shift = IDLXORP_ARM_SHIFT, 164 }; 165 166 static struct arm_idlect1_clk armtim_ck = { 167 .clk = { 168 .name = "armtim_ck", 169 .ops = &clkops_generic, 170 .parent = &ck_ref, 171 .flags = CLOCK_IDLE_CONTROL, 172 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 173 .enable_bit = EN_TIMCK, 174 .recalc = &followparent_recalc, 175 }, 176 .idlect_shift = IDLTIM_ARM_SHIFT, 177 }; 178 179 static struct arm_idlect1_clk armwdt_ck = { 180 .clk = { 181 .name = "armwdt_ck", 182 .ops = &clkops_generic, 183 .parent = &ck_ref, 184 .flags = CLOCK_IDLE_CONTROL, 185 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 186 .enable_bit = EN_WDTCK, 187 .fixed_div = 14, 188 .recalc = &omap_fixed_divisor_recalc, 189 }, 190 .idlect_shift = IDLWDT_ARM_SHIFT, 191 }; 192 193 static struct clk arminth_ck16xx = { 194 .name = "arminth_ck", 195 .ops = &clkops_null, 196 .parent = &arm_ck, 197 .recalc = &followparent_recalc, 198 /* Note: On 16xx the frequency can be divided by 2 by programming 199 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 200 * 201 * 1510 version is in TC clocks. 202 */ 203 }; 204 205 static struct clk dsp_ck = { 206 .name = "dsp_ck", 207 .ops = &clkops_generic, 208 .parent = &ck_dpll1, 209 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), 210 .enable_bit = EN_DSPCK, 211 .rate_offset = CKCTL_DSPDIV_OFFSET, 212 .recalc = &omap1_ckctl_recalc, 213 .round_rate = omap1_clk_round_rate_ckctl_arm, 214 .set_rate = omap1_clk_set_rate_ckctl_arm, 215 }; 216 217 static struct clk dspmmu_ck = { 218 .name = "dspmmu_ck", 219 .ops = &clkops_null, 220 .parent = &ck_dpll1, 221 .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 222 .recalc = &omap1_ckctl_recalc, 223 .round_rate = omap1_clk_round_rate_ckctl_arm, 224 .set_rate = omap1_clk_set_rate_ckctl_arm, 225 }; 226 227 static struct clk dspper_ck = { 228 .name = "dspper_ck", 229 .ops = &clkops_dspck, 230 .parent = &ck_dpll1, 231 .enable_reg = DSP_IDLECT2, 232 .enable_bit = EN_PERCK, 233 .rate_offset = CKCTL_PERDIV_OFFSET, 234 .recalc = &omap1_ckctl_recalc_dsp_domain, 235 .round_rate = omap1_clk_round_rate_ckctl_arm, 236 .set_rate = &omap1_clk_set_rate_dsp_domain, 237 }; 238 239 static struct clk dspxor_ck = { 240 .name = "dspxor_ck", 241 .ops = &clkops_dspck, 242 .parent = &ck_ref, 243 .enable_reg = DSP_IDLECT2, 244 .enable_bit = EN_XORPCK, 245 .recalc = &followparent_recalc, 246 }; 247 248 static struct clk dsptim_ck = { 249 .name = "dsptim_ck", 250 .ops = &clkops_dspck, 251 .parent = &ck_ref, 252 .enable_reg = DSP_IDLECT2, 253 .enable_bit = EN_DSPTIMCK, 254 .recalc = &followparent_recalc, 255 }; 256 257 static struct arm_idlect1_clk tc_ck = { 258 .clk = { 259 .name = "tc_ck", 260 .ops = &clkops_null, 261 .parent = &ck_dpll1, 262 .flags = CLOCK_IDLE_CONTROL, 263 .rate_offset = CKCTL_TCDIV_OFFSET, 264 .recalc = &omap1_ckctl_recalc, 265 .round_rate = omap1_clk_round_rate_ckctl_arm, 266 .set_rate = omap1_clk_set_rate_ckctl_arm, 267 }, 268 .idlect_shift = IDLIF_ARM_SHIFT, 269 }; 270 271 static struct clk arminth_ck1510 = { 272 .name = "arminth_ck", 273 .ops = &clkops_null, 274 .parent = &tc_ck.clk, 275 .recalc = &followparent_recalc, 276 /* Note: On 1510 the frequency follows TC_CK 277 * 278 * 16xx version is in MPU clocks. 279 */ 280 }; 281 282 static struct clk tipb_ck = { 283 /* No-idle controlled by "tc_ck" */ 284 .name = "tipb_ck", 285 .ops = &clkops_null, 286 .parent = &tc_ck.clk, 287 .recalc = &followparent_recalc, 288 }; 289 290 static struct clk l3_ocpi_ck = { 291 /* No-idle controlled by "tc_ck" */ 292 .name = "l3_ocpi_ck", 293 .ops = &clkops_generic, 294 .parent = &tc_ck.clk, 295 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), 296 .enable_bit = EN_OCPI_CK, 297 .recalc = &followparent_recalc, 298 }; 299 300 static struct clk tc1_ck = { 301 .name = "tc1_ck", 302 .ops = &clkops_generic, 303 .parent = &tc_ck.clk, 304 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), 305 .enable_bit = EN_TC1_CK, 306 .recalc = &followparent_recalc, 307 }; 308 309 /* 310 * FIXME: This clock seems to be necessary but no-one has asked for its 311 * activation. [ pm.c (SRAM), CCP, Camera ] 312 */ 313 static struct clk tc2_ck = { 314 .name = "tc2_ck", 315 .ops = &clkops_generic, 316 .parent = &tc_ck.clk, 317 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), 318 .enable_bit = EN_TC2_CK, 319 .recalc = &followparent_recalc, 320 }; 321 322 static struct clk dma_ck = { 323 /* No-idle controlled by "tc_ck" */ 324 .name = "dma_ck", 325 .ops = &clkops_null, 326 .parent = &tc_ck.clk, 327 .recalc = &followparent_recalc, 328 }; 329 330 static struct clk dma_lcdfree_ck = { 331 .name = "dma_lcdfree_ck", 332 .ops = &clkops_null, 333 .parent = &tc_ck.clk, 334 .recalc = &followparent_recalc, 335 }; 336 337 static struct arm_idlect1_clk api_ck = { 338 .clk = { 339 .name = "api_ck", 340 .ops = &clkops_generic, 341 .parent = &tc_ck.clk, 342 .flags = CLOCK_IDLE_CONTROL, 343 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 344 .enable_bit = EN_APICK, 345 .recalc = &followparent_recalc, 346 }, 347 .idlect_shift = IDLAPI_ARM_SHIFT, 348 }; 349 350 static struct arm_idlect1_clk lb_ck = { 351 .clk = { 352 .name = "lb_ck", 353 .ops = &clkops_generic, 354 .parent = &tc_ck.clk, 355 .flags = CLOCK_IDLE_CONTROL, 356 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 357 .enable_bit = EN_LBCK, 358 .recalc = &followparent_recalc, 359 }, 360 .idlect_shift = IDLLB_ARM_SHIFT, 361 }; 362 363 static struct clk rhea1_ck = { 364 .name = "rhea1_ck", 365 .ops = &clkops_null, 366 .parent = &tc_ck.clk, 367 .recalc = &followparent_recalc, 368 }; 369 370 static struct clk rhea2_ck = { 371 .name = "rhea2_ck", 372 .ops = &clkops_null, 373 .parent = &tc_ck.clk, 374 .recalc = &followparent_recalc, 375 }; 376 377 static struct clk lcd_ck_16xx = { 378 .name = "lcd_ck", 379 .ops = &clkops_generic, 380 .parent = &ck_dpll1, 381 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 382 .enable_bit = EN_LCDCK, 383 .rate_offset = CKCTL_LCDDIV_OFFSET, 384 .recalc = &omap1_ckctl_recalc, 385 .round_rate = omap1_clk_round_rate_ckctl_arm, 386 .set_rate = omap1_clk_set_rate_ckctl_arm, 387 }; 388 389 static struct arm_idlect1_clk lcd_ck_1510 = { 390 .clk = { 391 .name = "lcd_ck", 392 .ops = &clkops_generic, 393 .parent = &ck_dpll1, 394 .flags = CLOCK_IDLE_CONTROL, 395 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 396 .enable_bit = EN_LCDCK, 397 .rate_offset = CKCTL_LCDDIV_OFFSET, 398 .recalc = &omap1_ckctl_recalc, 399 .round_rate = omap1_clk_round_rate_ckctl_arm, 400 .set_rate = omap1_clk_set_rate_ckctl_arm, 401 }, 402 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, 403 }; 404 405 /* 406 * XXX The enable_bit here is misused - it simply switches between 12MHz 407 * and 48MHz. Reimplement with clksel. 408 * 409 * XXX does this need SYSC register handling? 410 */ 411 static struct clk uart1_1510 = { 412 .name = "uart1_ck", 413 .ops = &clkops_null, 414 /* Direct from ULPD, no real parent */ 415 .parent = &armper_ck.clk, 416 .rate = 12000000, 417 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 418 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 419 .enable_bit = CONF_MOD_UART1_CLK_MODE_R, 420 .set_rate = &omap1_set_uart_rate, 421 .recalc = &omap1_uart_recalc, 422 }; 423 424 /* 425 * XXX The enable_bit here is misused - it simply switches between 12MHz 426 * and 48MHz. Reimplement with clksel. 427 * 428 * XXX SYSC register handling does not belong in the clock framework 429 */ 430 static struct uart_clk uart1_16xx = { 431 .clk = { 432 .name = "uart1_ck", 433 .ops = &clkops_uart_16xx, 434 /* Direct from ULPD, no real parent */ 435 .parent = &armper_ck.clk, 436 .rate = 48000000, 437 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 438 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 439 .enable_bit = CONF_MOD_UART1_CLK_MODE_R, 440 }, 441 .sysc_addr = 0xfffb0054, 442 }; 443 444 /* 445 * XXX The enable_bit here is misused - it simply switches between 12MHz 446 * and 48MHz. Reimplement with clksel. 447 * 448 * XXX does this need SYSC register handling? 449 */ 450 static struct clk uart2_ck = { 451 .name = "uart2_ck", 452 .ops = &clkops_null, 453 /* Direct from ULPD, no real parent */ 454 .parent = &armper_ck.clk, 455 .rate = 12000000, 456 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 457 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 458 .enable_bit = CONF_MOD_UART2_CLK_MODE_R, 459 .set_rate = &omap1_set_uart_rate, 460 .recalc = &omap1_uart_recalc, 461 }; 462 463 /* 464 * XXX The enable_bit here is misused - it simply switches between 12MHz 465 * and 48MHz. Reimplement with clksel. 466 * 467 * XXX does this need SYSC register handling? 468 */ 469 static struct clk uart3_1510 = { 470 .name = "uart3_ck", 471 .ops = &clkops_null, 472 /* Direct from ULPD, no real parent */ 473 .parent = &armper_ck.clk, 474 .rate = 12000000, 475 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 476 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 477 .enable_bit = CONF_MOD_UART3_CLK_MODE_R, 478 .set_rate = &omap1_set_uart_rate, 479 .recalc = &omap1_uart_recalc, 480 }; 481 482 /* 483 * XXX The enable_bit here is misused - it simply switches between 12MHz 484 * and 48MHz. Reimplement with clksel. 485 * 486 * XXX SYSC register handling does not belong in the clock framework 487 */ 488 static struct uart_clk uart3_16xx = { 489 .clk = { 490 .name = "uart3_ck", 491 .ops = &clkops_uart_16xx, 492 /* Direct from ULPD, no real parent */ 493 .parent = &armper_ck.clk, 494 .rate = 48000000, 495 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 496 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 497 .enable_bit = CONF_MOD_UART3_CLK_MODE_R, 498 }, 499 .sysc_addr = 0xfffb9854, 500 }; 501 502 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 503 .name = "usb_clko", 504 .ops = &clkops_generic, 505 /* Direct from ULPD, no parent */ 506 .rate = 6000000, 507 .flags = ENABLE_REG_32BIT, 508 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), 509 .enable_bit = USB_MCLK_EN_BIT, 510 }; 511 512 static struct clk usb_hhc_ck1510 = { 513 .name = "usb_hhc_ck", 514 .ops = &clkops_generic, 515 /* Direct from ULPD, no parent */ 516 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 517 .flags = ENABLE_REG_32BIT, 518 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 519 .enable_bit = USB_HOST_HHC_UHOST_EN, 520 }; 521 522 static struct clk usb_hhc_ck16xx = { 523 .name = "usb_hhc_ck", 524 .ops = &clkops_generic, 525 /* Direct from ULPD, no parent */ 526 .rate = 48000000, 527 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 528 .flags = ENABLE_REG_32BIT, 529 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ 530 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT 531 }; 532 533 static struct clk usb_dc_ck = { 534 .name = "usb_dc_ck", 535 .ops = &clkops_generic, 536 /* Direct from ULPD, no parent */ 537 .rate = 48000000, 538 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 539 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, 540 }; 541 542 static struct clk uart1_7xx = { 543 .name = "uart1_ck", 544 .ops = &clkops_generic, 545 /* Direct from ULPD, no parent */ 546 .rate = 12000000, 547 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 548 .enable_bit = 9, 549 }; 550 551 static struct clk uart2_7xx = { 552 .name = "uart2_ck", 553 .ops = &clkops_generic, 554 /* Direct from ULPD, no parent */ 555 .rate = 12000000, 556 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 557 .enable_bit = 11, 558 }; 559 560 static struct clk mclk_1510 = { 561 .name = "mclk", 562 .ops = &clkops_generic, 563 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 564 .rate = 12000000, 565 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 566 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, 567 }; 568 569 static struct clk mclk_16xx = { 570 .name = "mclk", 571 .ops = &clkops_generic, 572 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 573 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), 574 .enable_bit = COM_ULPD_PLL_CLK_REQ, 575 .set_rate = &omap1_set_ext_clk_rate, 576 .round_rate = &omap1_round_ext_clk_rate, 577 .init = &omap1_init_ext_clk, 578 }; 579 580 static struct clk bclk_1510 = { 581 .name = "bclk", 582 .ops = &clkops_generic, 583 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 584 .rate = 12000000, 585 }; 586 587 static struct clk bclk_16xx = { 588 .name = "bclk", 589 .ops = &clkops_generic, 590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 591 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), 592 .enable_bit = SWD_ULPD_PLL_CLK_REQ, 593 .set_rate = &omap1_set_ext_clk_rate, 594 .round_rate = &omap1_round_ext_clk_rate, 595 .init = &omap1_init_ext_clk, 596 }; 597 598 static struct clk mmc1_ck = { 599 .name = "mmc1_ck", 600 .ops = &clkops_generic, 601 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 602 .parent = &armper_ck.clk, 603 .rate = 48000000, 604 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 605 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 606 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, 607 }; 608 609 /* 610 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as 611 * CONF_MOD_MCBSP3_AUXON ?? 612 */ 613 static struct clk mmc2_ck = { 614 .name = "mmc2_ck", 615 .ops = &clkops_generic, 616 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 617 .parent = &armper_ck.clk, 618 .rate = 48000000, 619 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 620 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 621 .enable_bit = 20, 622 }; 623 624 static struct clk mmc3_ck = { 625 .name = "mmc3_ck", 626 .ops = &clkops_generic, 627 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 628 .parent = &armper_ck.clk, 629 .rate = 48000000, 630 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 631 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 632 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, 633 }; 634 635 static struct clk virtual_ck_mpu = { 636 .name = "mpu", 637 .ops = &clkops_null, 638 .parent = &arm_ck, /* Is smarter alias for */ 639 .recalc = &followparent_recalc, 640 .set_rate = &omap1_select_table_rate, 641 .round_rate = &omap1_round_to_table_rate, 642 }; 643 644 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK 645 remains active during MPU idle whenever this is enabled */ 646 static struct clk i2c_fck = { 647 .name = "i2c_fck", 648 .ops = &clkops_null, 649 .flags = CLOCK_NO_IDLE_PARENT, 650 .parent = &armxor_ck.clk, 651 .recalc = &followparent_recalc, 652 }; 653 654 static struct clk i2c_ick = { 655 .name = "i2c_ick", 656 .ops = &clkops_null, 657 .flags = CLOCK_NO_IDLE_PARENT, 658 .parent = &armper_ck.clk, 659 .recalc = &followparent_recalc, 660 }; 661 662 /* 663 * clkdev integration 664 */ 665 666 static struct omap_clk omap_clks[] = { 667 /* non-ULPD clocks */ 668 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), 669 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), 670 /* CK_GEN1 clocks */ 671 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), 672 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), 673 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), 674 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 675 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), 676 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 677 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), 678 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), 679 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), 680 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), 681 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), 682 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), 683 /* CK_GEN2 clocks */ 684 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), 685 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), 686 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), 687 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 688 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), 689 /* CK_GEN3 clocks */ 690 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 691 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), 692 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), 693 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), 694 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), 695 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), 696 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), 697 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 698 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), 699 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), 700 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), 701 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), 702 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), 703 /* ULPD clocks */ 704 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), 705 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), 706 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), 707 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), 708 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), 709 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), 710 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), 711 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), 712 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), 713 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), 714 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), 715 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), 716 CLK(NULL, "mclk", &mclk_16xx, CK_16XX), 717 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), 718 CLK(NULL, "bclk", &bclk_16xx, CK_16XX), 719 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), 720 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), 721 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 722 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), 723 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), 724 /* Virtual clocks */ 725 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), 726 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), 727 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), 728 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), 729 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), 730 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), 731 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), 732 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), 733 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), 734 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), 735 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), 736 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), 737 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), 738 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), 739 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), 740 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 741 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 742 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 743 }; 744 745 /* 746 * init 747 */ 748 749 static void __init omap1_show_rates(void) 750 { 751 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 752 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, 753 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 754 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 755 } 756 757 u32 cpu_mask; 758 759 int __init omap1_clk_init(void) 760 { 761 struct omap_clk *c; 762 u32 reg; 763 764 #ifdef CONFIG_DEBUG_LL 765 /* Make sure UART clocks are enabled early */ 766 if (cpu_is_omap16xx()) 767 omap_writel(omap_readl(MOD_CONF_CTRL_0) | 768 CONF_MOD_UART1_CLK_MODE_R | 769 CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0); 770 #endif 771 772 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 773 reg = omap_readw(SOFT_REQ_REG) & (1 << 4); 774 omap_writew(reg, SOFT_REQ_REG); 775 if (!cpu_is_omap15xx()) 776 omap_writew(0, SOFT_REQ_REG2); 777 778 /* By default all idlect1 clocks are allowed to idle */ 779 arm_idlect1_mask = ~0; 780 781 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 782 clk_preinit(c->lk.clk); 783 784 cpu_mask = 0; 785 if (cpu_is_omap1710()) 786 cpu_mask |= CK_1710; 787 if (cpu_is_omap16xx()) 788 cpu_mask |= CK_16XX; 789 if (cpu_is_omap1510()) 790 cpu_mask |= CK_1510; 791 if (cpu_is_omap7xx()) 792 cpu_mask |= CK_7XX; 793 if (cpu_is_omap310()) 794 cpu_mask |= CK_310; 795 796 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 797 if (c->cpu & cpu_mask) { 798 clkdev_add(&c->lk); 799 clk_register(c->lk.clk); 800 } 801 802 /* Pointers to these clocks are needed by code in clock.c */ 803 api_ck_p = clk_get(NULL, "api_ck"); 804 ck_dpll1_p = clk_get(NULL, "ck_dpll1"); 805 ck_ref_p = clk_get(NULL, "ck_ref"); 806 807 if (cpu_is_omap7xx()) 808 ck_ref.rate = 13000000; 809 810 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", 811 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), 812 omap_readw(ARM_CKCTL)); 813 814 /* We want to be in synchronous scalable mode */ 815 omap_writew(0x1000, ARM_SYSST); 816 817 818 /* 819 * Initially use the values set by bootloader. Determine PLL rate and 820 * recalculate dependent clocks as if kernel had changed PLL or 821 * divisors. See also omap1_clk_late_init() that can reprogram dpll1 822 * after the SRAM is initialized. 823 */ 824 { 825 unsigned pll_ctl_val = omap_readw(DPLL_CTL); 826 827 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ 828 if (pll_ctl_val & 0x10) { 829 /* PLL enabled, apply multiplier and divisor */ 830 if (pll_ctl_val & 0xf80) 831 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; 832 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; 833 } else { 834 /* PLL disabled, apply bypass divisor */ 835 switch (pll_ctl_val & 0xc) { 836 case 0: 837 break; 838 case 0x4: 839 ck_dpll1.rate /= 2; 840 break; 841 default: 842 ck_dpll1.rate /= 4; 843 break; 844 } 845 } 846 } 847 propagate_rate(&ck_dpll1); 848 /* Cache rates for clocks connected to ck_ref (not dpll1) */ 849 propagate_rate(&ck_ref); 850 omap1_show_rates(); 851 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { 852 /* Select slicer output as OMAP input clock */ 853 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, 854 OMAP7XX_PCC_UPLD_CTRL); 855 } 856 857 /* Amstrad Delta wants BCLK high when inactive */ 858 if (machine_is_ams_delta()) 859 omap_writel(omap_readl(ULPD_CLOCK_CTRL) | 860 (1 << SDW_MCLK_INV_BIT), 861 ULPD_CLOCK_CTRL); 862 863 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 864 /* (on 730, bit 13 must not be cleared) */ 865 if (cpu_is_omap7xx()) 866 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 867 else 868 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 869 870 /* Put DSP/MPUI into reset until needed */ 871 omap_writew(0, ARM_RSTCT1); 872 omap_writew(1, ARM_RSTCT2); 873 omap_writew(0x400, ARM_IDLECT1); 874 875 /* 876 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) 877 * of the ARM_IDLECT2 register must be set to zero. The power-on 878 * default value of this bit is one. 879 */ 880 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ 881 882 /* 883 * Only enable those clocks we will need, let the drivers 884 * enable other clocks as necessary 885 */ 886 clk_enable(&armper_ck.clk); 887 clk_enable(&armxor_ck.clk); 888 clk_enable(&armtim_ck.clk); /* This should be done by timer code */ 889 890 if (cpu_is_omap15xx()) 891 clk_enable(&arm_gpio_ck); 892 893 return 0; 894 } 895 896 #define OMAP1_DPLL1_SANE_VALUE 60000000 897 898 void __init omap1_clk_late_init(void) 899 { 900 unsigned long rate = ck_dpll1.rate; 901 902 /* Find the highest supported frequency and enable it */ 903 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 904 pr_err("System frequencies not set, using default. Check your config.\n"); 905 /* 906 * Reprogramming the DPLL is tricky, it must be done from SRAM. 907 */ 908 omap_sram_reprogram_clock(0x2290, 0x0005); 909 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; 910 } 911 propagate_rate(&ck_dpll1); 912 omap1_show_rates(); 913 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); 914 } 915