1 /* 2 * linux/arch/arm/mach-omap1/clock.h 3 * 4 * Copyright (C) 2004 - 2005 Nokia corporation 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H 14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H 15 16 static int omap1_clk_enable_generic(struct clk * clk); 17 static void omap1_clk_disable_generic(struct clk * clk); 18 static void omap1_ckctl_recalc(struct clk * clk); 19 static void omap1_watchdog_recalc(struct clk * clk); 20 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); 21 static void omap1_sossi_recalc(struct clk *clk); 22 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); 23 static int omap1_clk_enable_dsp_domain(struct clk * clk); 24 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); 25 static void omap1_clk_disable_dsp_domain(struct clk * clk); 26 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); 27 static void omap1_uart_recalc(struct clk * clk); 28 static int omap1_clk_enable_uart_functional(struct clk * clk); 29 static void omap1_clk_disable_uart_functional(struct clk * clk); 30 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); 31 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); 32 static void omap1_init_ext_clk(struct clk * clk); 33 static int omap1_select_table_rate(struct clk * clk, unsigned long rate); 34 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); 35 static int omap1_clk_enable(struct clk *clk); 36 static void omap1_clk_disable(struct clk *clk); 37 38 struct mpu_rate { 39 unsigned long rate; 40 unsigned long xtal; 41 unsigned long pll_rate; 42 __u16 ckctl_val; 43 __u16 dpllctl_val; 44 }; 45 46 struct uart_clk { 47 struct clk clk; 48 unsigned long sysc_addr; 49 }; 50 51 /* Provide a method for preventing idling some ARM IDLECT clocks */ 52 struct arm_idlect1_clk { 53 struct clk clk; 54 unsigned long no_idle_count; 55 __u8 idlect_shift; 56 }; 57 58 /* ARM_CKCTL bit shifts */ 59 #define CKCTL_PERDIV_OFFSET 0 60 #define CKCTL_LCDDIV_OFFSET 2 61 #define CKCTL_ARMDIV_OFFSET 4 62 #define CKCTL_DSPDIV_OFFSET 6 63 #define CKCTL_TCDIV_OFFSET 8 64 #define CKCTL_DSPMMUDIV_OFFSET 10 65 /*#define ARM_TIMXO 12*/ 66 #define EN_DSPCK 13 67 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ 68 /* DSP_CKCTL bit shifts */ 69 #define CKCTL_DSPPERDIV_OFFSET 0 70 71 /* ARM_IDLECT2 bit shifts */ 72 #define EN_WDTCK 0 73 #define EN_XORPCK 1 74 #define EN_PERCK 2 75 #define EN_LCDCK 3 76 #define EN_LBCK 4 /* Not on 1610/1710 */ 77 /*#define EN_HSABCK 5*/ 78 #define EN_APICK 6 79 #define EN_TIMCK 7 80 #define DMACK_REQ 8 81 #define EN_GPIOCK 9 /* Not on 1610/1710 */ 82 /*#define EN_LBFREECK 10*/ 83 #define EN_CKOUT_ARM 11 84 85 /* ARM_IDLECT3 bit shifts */ 86 #define EN_OCPI_CK 0 87 #define EN_TC1_CK 2 88 #define EN_TC2_CK 4 89 90 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ 91 #define EN_DSPTIMCK 5 92 93 /* Various register defines for clock controls scattered around OMAP chip */ 94 #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ 95 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ 96 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ 97 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ 98 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ 99 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 100 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 101 #define SOFT_REQ_REG 0xfffe0834 102 #define SOFT_REQ_REG2 0xfffe0880 103 104 /*------------------------------------------------------------------------- 105 * Omap1 MPU rate table 106 *-------------------------------------------------------------------------*/ 107 static struct mpu_rate rate_table[] = { 108 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL 109 * NOTE: Comment order here is different from bits in CKCTL value: 110 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv 111 */ 112 #if defined(CONFIG_OMAP_ARM_216MHZ) 113 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ 114 #endif 115 #if defined(CONFIG_OMAP_ARM_195MHZ) 116 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ 117 #endif 118 #if defined(CONFIG_OMAP_ARM_192MHZ) 119 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ 120 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ 121 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ 122 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ 123 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ 124 #endif 125 #if defined(CONFIG_OMAP_ARM_182MHZ) 126 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ 127 #endif 128 #if defined(CONFIG_OMAP_ARM_168MHZ) 129 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ 130 #endif 131 #if defined(CONFIG_OMAP_ARM_150MHZ) 132 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ 133 #endif 134 #if defined(CONFIG_OMAP_ARM_120MHZ) 135 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ 136 #endif 137 #if defined(CONFIG_OMAP_ARM_96MHZ) 138 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ 139 #endif 140 #if defined(CONFIG_OMAP_ARM_60MHZ) 141 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ 142 #endif 143 #if defined(CONFIG_OMAP_ARM_30MHZ) 144 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ 145 #endif 146 { 0, 0, 0, 0, 0 }, 147 }; 148 149 /*------------------------------------------------------------------------- 150 * Omap1 clocks 151 *-------------------------------------------------------------------------*/ 152 153 static struct clk ck_ref = { 154 .name = "ck_ref", 155 .rate = 12000000, 156 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 157 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 158 .enable = &omap1_clk_enable_generic, 159 .disable = &omap1_clk_disable_generic, 160 }; 161 162 static struct clk ck_dpll1 = { 163 .name = "ck_dpll1", 164 .parent = &ck_ref, 165 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 166 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED, 167 .enable = &omap1_clk_enable_generic, 168 .disable = &omap1_clk_disable_generic, 169 }; 170 171 static struct arm_idlect1_clk ck_dpll1out = { 172 .clk = { 173 .name = "ck_dpll1out", 174 .parent = &ck_dpll1, 175 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | 176 ENABLE_REG_32BIT | RATE_PROPAGATES, 177 .enable_reg = (void __iomem *)ARM_IDLECT2, 178 .enable_bit = EN_CKOUT_ARM, 179 .recalc = &followparent_recalc, 180 .enable = &omap1_clk_enable_generic, 181 .disable = &omap1_clk_disable_generic, 182 }, 183 .idlect_shift = 12, 184 }; 185 186 static struct clk sossi_ck = { 187 .name = "ck_sossi", 188 .parent = &ck_dpll1out.clk, 189 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | 190 ENABLE_REG_32BIT, 191 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, 192 .enable_bit = 16, 193 .recalc = &omap1_sossi_recalc, 194 .set_rate = &omap1_set_sossi_rate, 195 .enable = &omap1_clk_enable_generic, 196 .disable = &omap1_clk_disable_generic, 197 }; 198 199 static struct clk arm_ck = { 200 .name = "arm_ck", 201 .parent = &ck_dpll1, 202 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 203 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | 204 ALWAYS_ENABLED, 205 .rate_offset = CKCTL_ARMDIV_OFFSET, 206 .recalc = &omap1_ckctl_recalc, 207 .enable = &omap1_clk_enable_generic, 208 .disable = &omap1_clk_disable_generic, 209 }; 210 211 static struct arm_idlect1_clk armper_ck = { 212 .clk = { 213 .name = "armper_ck", 214 .parent = &ck_dpll1, 215 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 216 CLOCK_IN_OMAP310 | RATE_CKCTL | 217 CLOCK_IDLE_CONTROL, 218 .enable_reg = (void __iomem *)ARM_IDLECT2, 219 .enable_bit = EN_PERCK, 220 .rate_offset = CKCTL_PERDIV_OFFSET, 221 .recalc = &omap1_ckctl_recalc, 222 .enable = &omap1_clk_enable_generic, 223 .disable = &omap1_clk_disable_generic, 224 }, 225 .idlect_shift = 2, 226 }; 227 228 static struct clk arm_gpio_ck = { 229 .name = "arm_gpio_ck", 230 .parent = &ck_dpll1, 231 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, 232 .enable_reg = (void __iomem *)ARM_IDLECT2, 233 .enable_bit = EN_GPIOCK, 234 .recalc = &followparent_recalc, 235 .enable = &omap1_clk_enable_generic, 236 .disable = &omap1_clk_disable_generic, 237 }; 238 239 static struct arm_idlect1_clk armxor_ck = { 240 .clk = { 241 .name = "armxor_ck", 242 .parent = &ck_ref, 243 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 244 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 245 .enable_reg = (void __iomem *)ARM_IDLECT2, 246 .enable_bit = EN_XORPCK, 247 .recalc = &followparent_recalc, 248 .enable = &omap1_clk_enable_generic, 249 .disable = &omap1_clk_disable_generic, 250 }, 251 .idlect_shift = 1, 252 }; 253 254 static struct arm_idlect1_clk armtim_ck = { 255 .clk = { 256 .name = "armtim_ck", 257 .parent = &ck_ref, 258 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 259 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 260 .enable_reg = (void __iomem *)ARM_IDLECT2, 261 .enable_bit = EN_TIMCK, 262 .recalc = &followparent_recalc, 263 .enable = &omap1_clk_enable_generic, 264 .disable = &omap1_clk_disable_generic, 265 }, 266 .idlect_shift = 9, 267 }; 268 269 static struct arm_idlect1_clk armwdt_ck = { 270 .clk = { 271 .name = "armwdt_ck", 272 .parent = &ck_ref, 273 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 274 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 275 .enable_reg = (void __iomem *)ARM_IDLECT2, 276 .enable_bit = EN_WDTCK, 277 .recalc = &omap1_watchdog_recalc, 278 .enable = &omap1_clk_enable_generic, 279 .disable = &omap1_clk_disable_generic, 280 }, 281 .idlect_shift = 0, 282 }; 283 284 static struct clk arminth_ck16xx = { 285 .name = "arminth_ck", 286 .parent = &arm_ck, 287 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 288 .recalc = &followparent_recalc, 289 /* Note: On 16xx the frequency can be divided by 2 by programming 290 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 291 * 292 * 1510 version is in TC clocks. 293 */ 294 .enable = &omap1_clk_enable_generic, 295 .disable = &omap1_clk_disable_generic, 296 }; 297 298 static struct clk dsp_ck = { 299 .name = "dsp_ck", 300 .parent = &ck_dpll1, 301 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 302 RATE_CKCTL, 303 .enable_reg = (void __iomem *)ARM_CKCTL, 304 .enable_bit = EN_DSPCK, 305 .rate_offset = CKCTL_DSPDIV_OFFSET, 306 .recalc = &omap1_ckctl_recalc, 307 .enable = &omap1_clk_enable_generic, 308 .disable = &omap1_clk_disable_generic, 309 }; 310 311 static struct clk dspmmu_ck = { 312 .name = "dspmmu_ck", 313 .parent = &ck_dpll1, 314 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 315 RATE_CKCTL | ALWAYS_ENABLED, 316 .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 317 .recalc = &omap1_ckctl_recalc, 318 .enable = &omap1_clk_enable_generic, 319 .disable = &omap1_clk_disable_generic, 320 }; 321 322 static struct clk dspper_ck = { 323 .name = "dspper_ck", 324 .parent = &ck_dpll1, 325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 326 RATE_CKCTL | VIRTUAL_IO_ADDRESS, 327 .enable_reg = (void __iomem *)DSP_IDLECT2, 328 .enable_bit = EN_PERCK, 329 .rate_offset = CKCTL_PERDIV_OFFSET, 330 .recalc = &omap1_ckctl_recalc_dsp_domain, 331 .set_rate = &omap1_clk_set_rate_dsp_domain, 332 .enable = &omap1_clk_enable_dsp_domain, 333 .disable = &omap1_clk_disable_dsp_domain, 334 }; 335 336 static struct clk dspxor_ck = { 337 .name = "dspxor_ck", 338 .parent = &ck_ref, 339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 340 VIRTUAL_IO_ADDRESS, 341 .enable_reg = (void __iomem *)DSP_IDLECT2, 342 .enable_bit = EN_XORPCK, 343 .recalc = &followparent_recalc, 344 .enable = &omap1_clk_enable_dsp_domain, 345 .disable = &omap1_clk_disable_dsp_domain, 346 }; 347 348 static struct clk dsptim_ck = { 349 .name = "dsptim_ck", 350 .parent = &ck_ref, 351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 352 VIRTUAL_IO_ADDRESS, 353 .enable_reg = (void __iomem *)DSP_IDLECT2, 354 .enable_bit = EN_DSPTIMCK, 355 .recalc = &followparent_recalc, 356 .enable = &omap1_clk_enable_dsp_domain, 357 .disable = &omap1_clk_disable_dsp_domain, 358 }; 359 360 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ 361 static struct arm_idlect1_clk tc_ck = { 362 .clk = { 363 .name = "tc_ck", 364 .parent = &ck_dpll1, 365 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 366 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | 367 RATE_CKCTL | RATE_PROPAGATES | 368 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, 369 .rate_offset = CKCTL_TCDIV_OFFSET, 370 .recalc = &omap1_ckctl_recalc, 371 .enable = &omap1_clk_enable_generic, 372 .disable = &omap1_clk_disable_generic, 373 }, 374 .idlect_shift = 6, 375 }; 376 377 static struct clk arminth_ck1510 = { 378 .name = "arminth_ck", 379 .parent = &tc_ck.clk, 380 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 381 ALWAYS_ENABLED, 382 .recalc = &followparent_recalc, 383 /* Note: On 1510 the frequency follows TC_CK 384 * 385 * 16xx version is in MPU clocks. 386 */ 387 .enable = &omap1_clk_enable_generic, 388 .disable = &omap1_clk_disable_generic, 389 }; 390 391 static struct clk tipb_ck = { 392 /* No-idle controlled by "tc_ck" */ 393 .name = "tipb_ck", 394 .parent = &tc_ck.clk, 395 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 396 ALWAYS_ENABLED, 397 .recalc = &followparent_recalc, 398 .enable = &omap1_clk_enable_generic, 399 .disable = &omap1_clk_disable_generic, 400 }; 401 402 static struct clk l3_ocpi_ck = { 403 /* No-idle controlled by "tc_ck" */ 404 .name = "l3_ocpi_ck", 405 .parent = &tc_ck.clk, 406 .flags = CLOCK_IN_OMAP16XX, 407 .enable_reg = (void __iomem *)ARM_IDLECT3, 408 .enable_bit = EN_OCPI_CK, 409 .recalc = &followparent_recalc, 410 .enable = &omap1_clk_enable_generic, 411 .disable = &omap1_clk_disable_generic, 412 }; 413 414 static struct clk tc1_ck = { 415 .name = "tc1_ck", 416 .parent = &tc_ck.clk, 417 .flags = CLOCK_IN_OMAP16XX, 418 .enable_reg = (void __iomem *)ARM_IDLECT3, 419 .enable_bit = EN_TC1_CK, 420 .recalc = &followparent_recalc, 421 .enable = &omap1_clk_enable_generic, 422 .disable = &omap1_clk_disable_generic, 423 }; 424 425 static struct clk tc2_ck = { 426 .name = "tc2_ck", 427 .parent = &tc_ck.clk, 428 .flags = CLOCK_IN_OMAP16XX, 429 .enable_reg = (void __iomem *)ARM_IDLECT3, 430 .enable_bit = EN_TC2_CK, 431 .recalc = &followparent_recalc, 432 .enable = &omap1_clk_enable_generic, 433 .disable = &omap1_clk_disable_generic, 434 }; 435 436 static struct clk dma_ck = { 437 /* No-idle controlled by "tc_ck" */ 438 .name = "dma_ck", 439 .parent = &tc_ck.clk, 440 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 441 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 442 .recalc = &followparent_recalc, 443 .enable = &omap1_clk_enable_generic, 444 .disable = &omap1_clk_disable_generic, 445 }; 446 447 static struct clk dma_lcdfree_ck = { 448 .name = "dma_lcdfree_ck", 449 .parent = &tc_ck.clk, 450 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 451 .recalc = &followparent_recalc, 452 .enable = &omap1_clk_enable_generic, 453 .disable = &omap1_clk_disable_generic, 454 }; 455 456 static struct arm_idlect1_clk api_ck = { 457 .clk = { 458 .name = "api_ck", 459 .parent = &tc_ck.clk, 460 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 461 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 462 .enable_reg = (void __iomem *)ARM_IDLECT2, 463 .enable_bit = EN_APICK, 464 .recalc = &followparent_recalc, 465 .enable = &omap1_clk_enable_generic, 466 .disable = &omap1_clk_disable_generic, 467 }, 468 .idlect_shift = 8, 469 }; 470 471 static struct arm_idlect1_clk lb_ck = { 472 .clk = { 473 .name = "lb_ck", 474 .parent = &tc_ck.clk, 475 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 476 CLOCK_IDLE_CONTROL, 477 .enable_reg = (void __iomem *)ARM_IDLECT2, 478 .enable_bit = EN_LBCK, 479 .recalc = &followparent_recalc, 480 .enable = &omap1_clk_enable_generic, 481 .disable = &omap1_clk_disable_generic, 482 }, 483 .idlect_shift = 4, 484 }; 485 486 static struct clk rhea1_ck = { 487 .name = "rhea1_ck", 488 .parent = &tc_ck.clk, 489 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 490 .recalc = &followparent_recalc, 491 .enable = &omap1_clk_enable_generic, 492 .disable = &omap1_clk_disable_generic, 493 }; 494 495 static struct clk rhea2_ck = { 496 .name = "rhea2_ck", 497 .parent = &tc_ck.clk, 498 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 499 .recalc = &followparent_recalc, 500 .enable = &omap1_clk_enable_generic, 501 .disable = &omap1_clk_disable_generic, 502 }; 503 504 static struct clk lcd_ck_16xx = { 505 .name = "lcd_ck", 506 .parent = &ck_dpll1, 507 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, 508 .enable_reg = (void __iomem *)ARM_IDLECT2, 509 .enable_bit = EN_LCDCK, 510 .rate_offset = CKCTL_LCDDIV_OFFSET, 511 .recalc = &omap1_ckctl_recalc, 512 .enable = &omap1_clk_enable_generic, 513 .disable = &omap1_clk_disable_generic, 514 }; 515 516 static struct arm_idlect1_clk lcd_ck_1510 = { 517 .clk = { 518 .name = "lcd_ck", 519 .parent = &ck_dpll1, 520 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 521 RATE_CKCTL | CLOCK_IDLE_CONTROL, 522 .enable_reg = (void __iomem *)ARM_IDLECT2, 523 .enable_bit = EN_LCDCK, 524 .rate_offset = CKCTL_LCDDIV_OFFSET, 525 .recalc = &omap1_ckctl_recalc, 526 .enable = &omap1_clk_enable_generic, 527 .disable = &omap1_clk_disable_generic, 528 }, 529 .idlect_shift = 3, 530 }; 531 532 static struct clk uart1_1510 = { 533 .name = "uart1_ck", 534 /* Direct from ULPD, no real parent */ 535 .parent = &armper_ck.clk, 536 .rate = 12000000, 537 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 538 ENABLE_REG_32BIT | ALWAYS_ENABLED | 539 CLOCK_NO_IDLE_PARENT, 540 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 541 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ 542 .set_rate = &omap1_set_uart_rate, 543 .recalc = &omap1_uart_recalc, 544 .enable = &omap1_clk_enable_generic, 545 .disable = &omap1_clk_disable_generic, 546 }; 547 548 static struct uart_clk uart1_16xx = { 549 .clk = { 550 .name = "uart1_ck", 551 /* Direct from ULPD, no real parent */ 552 .parent = &armper_ck.clk, 553 .rate = 48000000, 554 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 555 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 556 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 557 .enable_bit = 29, 558 .enable = &omap1_clk_enable_uart_functional, 559 .disable = &omap1_clk_disable_uart_functional, 560 }, 561 .sysc_addr = 0xfffb0054, 562 }; 563 564 static struct clk uart2_ck = { 565 .name = "uart2_ck", 566 /* Direct from ULPD, no real parent */ 567 .parent = &armper_ck.clk, 568 .rate = 12000000, 569 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 570 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | 571 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, 572 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 573 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ 574 .set_rate = &omap1_set_uart_rate, 575 .recalc = &omap1_uart_recalc, 576 .enable = &omap1_clk_enable_generic, 577 .disable = &omap1_clk_disable_generic, 578 }; 579 580 static struct clk uart3_1510 = { 581 .name = "uart3_ck", 582 /* Direct from ULPD, no real parent */ 583 .parent = &armper_ck.clk, 584 .rate = 12000000, 585 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 586 ENABLE_REG_32BIT | ALWAYS_ENABLED | 587 CLOCK_NO_IDLE_PARENT, 588 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 589 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ 590 .set_rate = &omap1_set_uart_rate, 591 .recalc = &omap1_uart_recalc, 592 .enable = &omap1_clk_enable_generic, 593 .disable = &omap1_clk_disable_generic, 594 }; 595 596 static struct uart_clk uart3_16xx = { 597 .clk = { 598 .name = "uart3_ck", 599 /* Direct from ULPD, no real parent */ 600 .parent = &armper_ck.clk, 601 .rate = 48000000, 602 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 603 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 604 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 605 .enable_bit = 31, 606 .enable = &omap1_clk_enable_uart_functional, 607 .disable = &omap1_clk_disable_uart_functional, 608 }, 609 .sysc_addr = 0xfffb9854, 610 }; 611 612 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 613 .name = "usb_clko", 614 /* Direct from ULPD, no parent */ 615 .rate = 6000000, 616 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 617 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT, 618 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, 619 .enable_bit = USB_MCLK_EN_BIT, 620 .enable = &omap1_clk_enable_generic, 621 .disable = &omap1_clk_disable_generic, 622 }; 623 624 static struct clk usb_hhc_ck1510 = { 625 .name = "usb_hhc_ck", 626 /* Direct from ULPD, no parent */ 627 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 628 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 629 RATE_FIXED | ENABLE_REG_32BIT, 630 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 631 .enable_bit = USB_HOST_HHC_UHOST_EN, 632 .enable = &omap1_clk_enable_generic, 633 .disable = &omap1_clk_disable_generic, 634 }; 635 636 static struct clk usb_hhc_ck16xx = { 637 .name = "usb_hhc_ck", 638 /* Direct from ULPD, no parent */ 639 .rate = 48000000, 640 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 641 .flags = CLOCK_IN_OMAP16XX | 642 RATE_FIXED | ENABLE_REG_32BIT, 643 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, 644 .enable_bit = 8 /* UHOST_EN */, 645 .enable = &omap1_clk_enable_generic, 646 .disable = &omap1_clk_disable_generic, 647 }; 648 649 static struct clk usb_dc_ck = { 650 .name = "usb_dc_ck", 651 /* Direct from ULPD, no parent */ 652 .rate = 48000000, 653 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, 654 .enable_reg = (void __iomem *)SOFT_REQ_REG, 655 .enable_bit = 4, 656 .enable = &omap1_clk_enable_generic, 657 .disable = &omap1_clk_disable_generic, 658 }; 659 660 static struct clk mclk_1510 = { 661 .name = "mclk", 662 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 663 .rate = 12000000, 664 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 665 .enable_reg = (void __iomem *)SOFT_REQ_REG, 666 .enable_bit = 6, 667 .enable = &omap1_clk_enable_generic, 668 .disable = &omap1_clk_disable_generic, 669 }; 670 671 static struct clk mclk_16xx = { 672 .name = "mclk", 673 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 674 .flags = CLOCK_IN_OMAP16XX, 675 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, 676 .enable_bit = COM_ULPD_PLL_CLK_REQ, 677 .set_rate = &omap1_set_ext_clk_rate, 678 .round_rate = &omap1_round_ext_clk_rate, 679 .init = &omap1_init_ext_clk, 680 .enable = &omap1_clk_enable_generic, 681 .disable = &omap1_clk_disable_generic, 682 }; 683 684 static struct clk bclk_1510 = { 685 .name = "bclk", 686 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 687 .rate = 12000000, 688 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 689 .enable = &omap1_clk_enable_generic, 690 .disable = &omap1_clk_disable_generic, 691 }; 692 693 static struct clk bclk_16xx = { 694 .name = "bclk", 695 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 696 .flags = CLOCK_IN_OMAP16XX, 697 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, 698 .enable_bit = SWD_ULPD_PLL_CLK_REQ, 699 .set_rate = &omap1_set_ext_clk_rate, 700 .round_rate = &omap1_round_ext_clk_rate, 701 .init = &omap1_init_ext_clk, 702 .enable = &omap1_clk_enable_generic, 703 .disable = &omap1_clk_disable_generic, 704 }; 705 706 static struct clk mmc1_ck = { 707 .name = "mmc_ck", 708 .id = 1, 709 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 710 .parent = &armper_ck.clk, 711 .rate = 48000000, 712 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 713 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT | 714 CLOCK_NO_IDLE_PARENT, 715 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 716 .enable_bit = 23, 717 .enable = &omap1_clk_enable_generic, 718 .disable = &omap1_clk_disable_generic, 719 }; 720 721 static struct clk mmc2_ck = { 722 .name = "mmc_ck", 723 .id = 2, 724 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 725 .parent = &armper_ck.clk, 726 .rate = 48000000, 727 .flags = CLOCK_IN_OMAP16XX | 728 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 729 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 730 .enable_bit = 20, 731 .enable = &omap1_clk_enable_generic, 732 .disable = &omap1_clk_disable_generic, 733 }; 734 735 static struct clk virtual_ck_mpu = { 736 .name = "mpu", 737 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 738 CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED, 739 .parent = &arm_ck, /* Is smarter alias for */ 740 .recalc = &followparent_recalc, 741 .set_rate = &omap1_select_table_rate, 742 .round_rate = &omap1_round_to_table_rate, 743 .enable = &omap1_clk_enable_generic, 744 .disable = &omap1_clk_disable_generic, 745 }; 746 747 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK 748 remains active during MPU idle whenever this is enabled */ 749 static struct clk i2c_fck = { 750 .name = "i2c_fck", 751 .id = 1, 752 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 753 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | 754 ALWAYS_ENABLED, 755 .parent = &armxor_ck.clk, 756 .recalc = &followparent_recalc, 757 .enable = &omap1_clk_enable_generic, 758 .disable = &omap1_clk_disable_generic, 759 }; 760 761 static struct clk i2c_ick = { 762 .name = "i2c_ick", 763 .id = 1, 764 .flags = CLOCK_IN_OMAP16XX | 765 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | 766 ALWAYS_ENABLED, 767 .parent = &armper_ck.clk, 768 .recalc = &followparent_recalc, 769 .enable = &omap1_clk_enable_generic, 770 .disable = &omap1_clk_disable_generic, 771 }; 772 773 static struct clk * onchip_clks[] = { 774 /* non-ULPD clocks */ 775 &ck_ref, 776 &ck_dpll1, 777 /* CK_GEN1 clocks */ 778 &ck_dpll1out.clk, 779 &sossi_ck, 780 &arm_ck, 781 &armper_ck.clk, 782 &arm_gpio_ck, 783 &armxor_ck.clk, 784 &armtim_ck.clk, 785 &armwdt_ck.clk, 786 &arminth_ck1510, &arminth_ck16xx, 787 /* CK_GEN2 clocks */ 788 &dsp_ck, 789 &dspmmu_ck, 790 &dspper_ck, 791 &dspxor_ck, 792 &dsptim_ck, 793 /* CK_GEN3 clocks */ 794 &tc_ck.clk, 795 &tipb_ck, 796 &l3_ocpi_ck, 797 &tc1_ck, 798 &tc2_ck, 799 &dma_ck, 800 &dma_lcdfree_ck, 801 &api_ck.clk, 802 &lb_ck.clk, 803 &rhea1_ck, 804 &rhea2_ck, 805 &lcd_ck_16xx, 806 &lcd_ck_1510.clk, 807 /* ULPD clocks */ 808 &uart1_1510, 809 &uart1_16xx.clk, 810 &uart2_ck, 811 &uart3_1510, 812 &uart3_16xx.clk, 813 &usb_clko, 814 &usb_hhc_ck1510, &usb_hhc_ck16xx, 815 &usb_dc_ck, 816 &mclk_1510, &mclk_16xx, 817 &bclk_1510, &bclk_16xx, 818 &mmc1_ck, 819 &mmc2_ck, 820 /* Virtual clocks */ 821 &virtual_ck_mpu, 822 &i2c_fck, 823 &i2c_ick, 824 }; 825 826 #endif 827