1 /* 2 * linux/arch/arm/mach-omap1/clock.c 3 * 4 * Copyright (C) 2004 - 2005 Nokia corporation 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 6 * 7 * Modified to use omap shared clock framework by 8 * Tony Lindgren <tony@atomide.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/list.h> 17 #include <linux/errno.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 22 #include <asm/mach-types.h> 23 24 #include <mach/cpu.h> 25 #include <mach/usb.h> 26 #include <mach/clock.h> 27 #include <mach/sram.h> 28 29 static const struct clkops clkops_generic; 30 static const struct clkops clkops_uart; 31 static const struct clkops clkops_dspck; 32 33 #include "clock.h" 34 35 static int omap1_clk_enable_generic(struct clk * clk); 36 static int omap1_clk_enable(struct clk *clk); 37 static void omap1_clk_disable_generic(struct clk * clk); 38 static void omap1_clk_disable(struct clk *clk); 39 40 __u32 arm_idlect1_mask; 41 42 /*------------------------------------------------------------------------- 43 * Omap1 specific clock functions 44 *-------------------------------------------------------------------------*/ 45 46 static void omap1_watchdog_recalc(struct clk * clk) 47 { 48 clk->rate = clk->parent->rate / 14; 49 } 50 51 static void omap1_uart_recalc(struct clk * clk) 52 { 53 unsigned int val = omap_readl(clk->enable_reg); 54 if (val & clk->enable_bit) 55 clk->rate = 48000000; 56 else 57 clk->rate = 12000000; 58 } 59 60 static void omap1_sossi_recalc(struct clk *clk) 61 { 62 u32 div = omap_readl(MOD_CONF_CTRL_1); 63 64 div = (div >> 17) & 0x7; 65 div++; 66 clk->rate = clk->parent->rate / div; 67 } 68 69 static int omap1_clk_enable_dsp_domain(struct clk *clk) 70 { 71 int retval; 72 73 retval = omap1_clk_enable(&api_ck.clk); 74 if (!retval) { 75 retval = omap1_clk_enable_generic(clk); 76 omap1_clk_disable(&api_ck.clk); 77 } 78 79 return retval; 80 } 81 82 static void omap1_clk_disable_dsp_domain(struct clk *clk) 83 { 84 if (omap1_clk_enable(&api_ck.clk) == 0) { 85 omap1_clk_disable_generic(clk); 86 omap1_clk_disable(&api_ck.clk); 87 } 88 } 89 90 static const struct clkops clkops_dspck = { 91 .enable = &omap1_clk_enable_dsp_domain, 92 .disable = &omap1_clk_disable_dsp_domain, 93 }; 94 95 static int omap1_clk_enable_uart_functional(struct clk *clk) 96 { 97 int ret; 98 struct uart_clk *uclk; 99 100 ret = omap1_clk_enable_generic(clk); 101 if (ret == 0) { 102 /* Set smart idle acknowledgement mode */ 103 uclk = (struct uart_clk *)clk; 104 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, 105 uclk->sysc_addr); 106 } 107 108 return ret; 109 } 110 111 static void omap1_clk_disable_uart_functional(struct clk *clk) 112 { 113 struct uart_clk *uclk; 114 115 /* Set force idle acknowledgement mode */ 116 uclk = (struct uart_clk *)clk; 117 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); 118 119 omap1_clk_disable_generic(clk); 120 } 121 122 static const struct clkops clkops_uart = { 123 .enable = &omap1_clk_enable_uart_functional, 124 .disable = &omap1_clk_disable_uart_functional, 125 }; 126 127 static void omap1_clk_allow_idle(struct clk *clk) 128 { 129 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 130 131 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 132 return; 133 134 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) 135 arm_idlect1_mask |= 1 << iclk->idlect_shift; 136 } 137 138 static void omap1_clk_deny_idle(struct clk *clk) 139 { 140 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 141 142 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 143 return; 144 145 if (iclk->no_idle_count++ == 0) 146 arm_idlect1_mask &= ~(1 << iclk->idlect_shift); 147 } 148 149 static __u16 verify_ckctl_value(__u16 newval) 150 { 151 /* This function checks for following limitations set 152 * by the hardware (all conditions must be true): 153 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 154 * ARM_CK >= TC_CK 155 * DSP_CK >= TC_CK 156 * DSPMMU_CK >= TC_CK 157 * 158 * In addition following rules are enforced: 159 * LCD_CK <= TC_CK 160 * ARMPER_CK <= TC_CK 161 * 162 * However, maximum frequencies are not checked for! 163 */ 164 __u8 per_exp; 165 __u8 lcd_exp; 166 __u8 arm_exp; 167 __u8 dsp_exp; 168 __u8 tc_exp; 169 __u8 dspmmu_exp; 170 171 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; 172 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; 173 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; 174 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; 175 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; 176 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; 177 178 if (dspmmu_exp < dsp_exp) 179 dspmmu_exp = dsp_exp; 180 if (dspmmu_exp > dsp_exp+1) 181 dspmmu_exp = dsp_exp+1; 182 if (tc_exp < arm_exp) 183 tc_exp = arm_exp; 184 if (tc_exp < dspmmu_exp) 185 tc_exp = dspmmu_exp; 186 if (tc_exp > lcd_exp) 187 lcd_exp = tc_exp; 188 if (tc_exp > per_exp) 189 per_exp = tc_exp; 190 191 newval &= 0xf000; 192 newval |= per_exp << CKCTL_PERDIV_OFFSET; 193 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; 194 newval |= arm_exp << CKCTL_ARMDIV_OFFSET; 195 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; 196 newval |= tc_exp << CKCTL_TCDIV_OFFSET; 197 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; 198 199 return newval; 200 } 201 202 static int calc_dsor_exp(struct clk *clk, unsigned long rate) 203 { 204 /* Note: If target frequency is too low, this function will return 4, 205 * which is invalid value. Caller must check for this value and act 206 * accordingly. 207 * 208 * Note: This function does not check for following limitations set 209 * by the hardware (all conditions must be true): 210 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 211 * ARM_CK >= TC_CK 212 * DSP_CK >= TC_CK 213 * DSPMMU_CK >= TC_CK 214 */ 215 unsigned long realrate; 216 struct clk * parent; 217 unsigned dsor_exp; 218 219 parent = clk->parent; 220 if (unlikely(parent == NULL)) 221 return -EIO; 222 223 realrate = parent->rate; 224 for (dsor_exp=0; dsor_exp<4; dsor_exp++) { 225 if (realrate <= rate) 226 break; 227 228 realrate /= 2; 229 } 230 231 return dsor_exp; 232 } 233 234 static void omap1_ckctl_recalc(struct clk * clk) 235 { 236 int dsor; 237 238 /* Calculate divisor encoded as 2-bit exponent */ 239 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 240 241 if (unlikely(clk->rate == clk->parent->rate / dsor)) 242 return; /* No change, quick exit */ 243 clk->rate = clk->parent->rate / dsor; 244 } 245 246 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) 247 { 248 int dsor; 249 250 /* Calculate divisor encoded as 2-bit exponent 251 * 252 * The clock control bits are in DSP domain, 253 * so api_ck is needed for access. 254 * Note that DSP_CKCTL virt addr = phys addr, so 255 * we must use __raw_readw() instead of omap_readw(). 256 */ 257 omap1_clk_enable(&api_ck.clk); 258 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); 259 omap1_clk_disable(&api_ck.clk); 260 261 if (unlikely(clk->rate == clk->parent->rate / dsor)) 262 return; /* No change, quick exit */ 263 clk->rate = clk->parent->rate / dsor; 264 } 265 266 /* MPU virtual clock functions */ 267 static int omap1_select_table_rate(struct clk * clk, unsigned long rate) 268 { 269 /* Find the highest supported frequency <= rate and switch to it */ 270 struct mpu_rate * ptr; 271 272 if (clk != &virtual_ck_mpu) 273 return -EINVAL; 274 275 for (ptr = rate_table; ptr->rate; ptr++) { 276 if (ptr->xtal != ck_ref.rate) 277 continue; 278 279 /* DPLL1 cannot be reprogrammed without risking system crash */ 280 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) 281 continue; 282 283 /* Can check only after xtal frequency check */ 284 if (ptr->rate <= rate) 285 break; 286 } 287 288 if (!ptr->rate) 289 return -EINVAL; 290 291 /* 292 * In most cases we should not need to reprogram DPLL. 293 * Reprogramming the DPLL is tricky, it must be done from SRAM. 294 * (on 730, bit 13 must always be 1) 295 */ 296 if (cpu_is_omap730()) 297 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); 298 else 299 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 300 301 ck_dpll1.rate = ptr->pll_rate; 302 return 0; 303 } 304 305 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) 306 { 307 int dsor_exp; 308 u16 regval; 309 310 dsor_exp = calc_dsor_exp(clk, rate); 311 if (dsor_exp > 3) 312 dsor_exp = -EINVAL; 313 if (dsor_exp < 0) 314 return dsor_exp; 315 316 regval = __raw_readw(DSP_CKCTL); 317 regval &= ~(3 << clk->rate_offset); 318 regval |= dsor_exp << clk->rate_offset; 319 __raw_writew(regval, DSP_CKCTL); 320 clk->rate = clk->parent->rate / (1 << dsor_exp); 321 322 return 0; 323 } 324 325 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) 326 { 327 int dsor_exp = calc_dsor_exp(clk, rate); 328 if (dsor_exp < 0) 329 return dsor_exp; 330 if (dsor_exp > 3) 331 dsor_exp = 3; 332 return clk->parent->rate / (1 << dsor_exp); 333 } 334 335 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) 336 { 337 int dsor_exp; 338 u16 regval; 339 340 dsor_exp = calc_dsor_exp(clk, rate); 341 if (dsor_exp > 3) 342 dsor_exp = -EINVAL; 343 if (dsor_exp < 0) 344 return dsor_exp; 345 346 regval = omap_readw(ARM_CKCTL); 347 regval &= ~(3 << clk->rate_offset); 348 regval |= dsor_exp << clk->rate_offset; 349 regval = verify_ckctl_value(regval); 350 omap_writew(regval, ARM_CKCTL); 351 clk->rate = clk->parent->rate / (1 << dsor_exp); 352 return 0; 353 } 354 355 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) 356 { 357 /* Find the highest supported frequency <= rate */ 358 struct mpu_rate * ptr; 359 long highest_rate; 360 361 if (clk != &virtual_ck_mpu) 362 return -EINVAL; 363 364 highest_rate = -EINVAL; 365 366 for (ptr = rate_table; ptr->rate; ptr++) { 367 if (ptr->xtal != ck_ref.rate) 368 continue; 369 370 highest_rate = ptr->rate; 371 372 /* Can check only after xtal frequency check */ 373 if (ptr->rate <= rate) 374 break; 375 } 376 377 return highest_rate; 378 } 379 380 static unsigned calc_ext_dsor(unsigned long rate) 381 { 382 unsigned dsor; 383 384 /* MCLK and BCLK divisor selection is not linear: 385 * freq = 96MHz / dsor 386 * 387 * RATIO_SEL range: dsor <-> RATIO_SEL 388 * 0..6: (RATIO_SEL+2) <-> (dsor-2) 389 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) 390 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 391 * can not be used. 392 */ 393 for (dsor = 2; dsor < 96; ++dsor) { 394 if ((dsor & 1) && dsor > 8) 395 continue; 396 if (rate >= 96000000 / dsor) 397 break; 398 } 399 return dsor; 400 } 401 402 /* Only needed on 1510 */ 403 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) 404 { 405 unsigned int val; 406 407 val = omap_readl(clk->enable_reg); 408 if (rate == 12000000) 409 val &= ~(1 << clk->enable_bit); 410 else if (rate == 48000000) 411 val |= (1 << clk->enable_bit); 412 else 413 return -EINVAL; 414 omap_writel(val, clk->enable_reg); 415 clk->rate = rate; 416 417 return 0; 418 } 419 420 /* External clock (MCLK & BCLK) functions */ 421 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) 422 { 423 unsigned dsor; 424 __u16 ratio_bits; 425 426 dsor = calc_ext_dsor(rate); 427 clk->rate = 96000000 / dsor; 428 if (dsor > 8) 429 ratio_bits = ((dsor - 8) / 2 + 6) << 2; 430 else 431 ratio_bits = (dsor - 2) << 2; 432 433 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; 434 omap_writew(ratio_bits, clk->enable_reg); 435 436 return 0; 437 } 438 439 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) 440 { 441 u32 l; 442 int div; 443 unsigned long p_rate; 444 445 p_rate = clk->parent->rate; 446 /* Round towards slower frequency */ 447 div = (p_rate + rate - 1) / rate; 448 div--; 449 if (div < 0 || div > 7) 450 return -EINVAL; 451 452 l = omap_readl(MOD_CONF_CTRL_1); 453 l &= ~(7 << 17); 454 l |= div << 17; 455 omap_writel(l, MOD_CONF_CTRL_1); 456 457 clk->rate = p_rate / (div + 1); 458 459 return 0; 460 } 461 462 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) 463 { 464 return 96000000 / calc_ext_dsor(rate); 465 } 466 467 static void omap1_init_ext_clk(struct clk * clk) 468 { 469 unsigned dsor; 470 __u16 ratio_bits; 471 472 /* Determine current rate and ensure clock is based on 96MHz APLL */ 473 ratio_bits = omap_readw(clk->enable_reg) & ~1; 474 omap_writew(ratio_bits, clk->enable_reg); 475 476 ratio_bits = (ratio_bits & 0xfc) >> 2; 477 if (ratio_bits > 6) 478 dsor = (ratio_bits - 6) * 2 + 8; 479 else 480 dsor = ratio_bits + 2; 481 482 clk-> rate = 96000000 / dsor; 483 } 484 485 static int omap1_clk_enable(struct clk *clk) 486 { 487 int ret = 0; 488 if (clk->usecount++ == 0) { 489 if (likely(clk->parent)) { 490 ret = omap1_clk_enable(clk->parent); 491 492 if (unlikely(ret != 0)) { 493 clk->usecount--; 494 return ret; 495 } 496 497 if (clk->flags & CLOCK_NO_IDLE_PARENT) 498 omap1_clk_deny_idle(clk->parent); 499 } 500 501 ret = clk->ops->enable(clk); 502 503 if (unlikely(ret != 0) && clk->parent) { 504 omap1_clk_disable(clk->parent); 505 clk->usecount--; 506 } 507 } 508 509 return ret; 510 } 511 512 static void omap1_clk_disable(struct clk *clk) 513 { 514 if (clk->usecount > 0 && !(--clk->usecount)) { 515 clk->ops->disable(clk); 516 if (likely(clk->parent)) { 517 omap1_clk_disable(clk->parent); 518 if (clk->flags & CLOCK_NO_IDLE_PARENT) 519 omap1_clk_allow_idle(clk->parent); 520 } 521 } 522 } 523 524 static int omap1_clk_enable_generic(struct clk *clk) 525 { 526 __u16 regval16; 527 __u32 regval32; 528 529 if (unlikely(clk->enable_reg == NULL)) { 530 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 531 clk->name); 532 return -EINVAL; 533 } 534 535 if (clk->flags & ENABLE_REG_32BIT) { 536 if (clk->flags & VIRTUAL_IO_ADDRESS) { 537 regval32 = __raw_readl(clk->enable_reg); 538 regval32 |= (1 << clk->enable_bit); 539 __raw_writel(regval32, clk->enable_reg); 540 } else { 541 regval32 = omap_readl(clk->enable_reg); 542 regval32 |= (1 << clk->enable_bit); 543 omap_writel(regval32, clk->enable_reg); 544 } 545 } else { 546 if (clk->flags & VIRTUAL_IO_ADDRESS) { 547 regval16 = __raw_readw(clk->enable_reg); 548 regval16 |= (1 << clk->enable_bit); 549 __raw_writew(regval16, clk->enable_reg); 550 } else { 551 regval16 = omap_readw(clk->enable_reg); 552 regval16 |= (1 << clk->enable_bit); 553 omap_writew(regval16, clk->enable_reg); 554 } 555 } 556 557 return 0; 558 } 559 560 static void omap1_clk_disable_generic(struct clk *clk) 561 { 562 __u16 regval16; 563 __u32 regval32; 564 565 if (clk->enable_reg == NULL) 566 return; 567 568 if (clk->flags & ENABLE_REG_32BIT) { 569 if (clk->flags & VIRTUAL_IO_ADDRESS) { 570 regval32 = __raw_readl(clk->enable_reg); 571 regval32 &= ~(1 << clk->enable_bit); 572 __raw_writel(regval32, clk->enable_reg); 573 } else { 574 regval32 = omap_readl(clk->enable_reg); 575 regval32 &= ~(1 << clk->enable_bit); 576 omap_writel(regval32, clk->enable_reg); 577 } 578 } else { 579 if (clk->flags & VIRTUAL_IO_ADDRESS) { 580 regval16 = __raw_readw(clk->enable_reg); 581 regval16 &= ~(1 << clk->enable_bit); 582 __raw_writew(regval16, clk->enable_reg); 583 } else { 584 regval16 = omap_readw(clk->enable_reg); 585 regval16 &= ~(1 << clk->enable_bit); 586 omap_writew(regval16, clk->enable_reg); 587 } 588 } 589 } 590 591 static const struct clkops clkops_generic = { 592 .enable = &omap1_clk_enable_generic, 593 .disable = &omap1_clk_disable_generic, 594 }; 595 596 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 597 { 598 if (clk->flags & RATE_FIXED) 599 return clk->rate; 600 601 if (clk->round_rate != NULL) 602 return clk->round_rate(clk, rate); 603 604 return clk->rate; 605 } 606 607 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) 608 { 609 int ret = -EINVAL; 610 611 if (clk->set_rate) 612 ret = clk->set_rate(clk, rate); 613 return ret; 614 } 615 616 /*------------------------------------------------------------------------- 617 * Omap1 clock reset and init functions 618 *-------------------------------------------------------------------------*/ 619 620 #ifdef CONFIG_OMAP_RESET_CLOCKS 621 622 static void __init omap1_clk_disable_unused(struct clk *clk) 623 { 624 __u32 regval32; 625 626 /* Clocks in the DSP domain need api_ck. Just assume bootloader 627 * has not enabled any DSP clocks */ 628 if (clk->enable_reg == DSP_IDLECT2) { 629 printk(KERN_INFO "Skipping reset check for DSP domain " 630 "clock \"%s\"\n", clk->name); 631 return; 632 } 633 634 /* Is the clock already disabled? */ 635 if (clk->flags & ENABLE_REG_32BIT) { 636 if (clk->flags & VIRTUAL_IO_ADDRESS) 637 regval32 = __raw_readl(clk->enable_reg); 638 else 639 regval32 = omap_readl(clk->enable_reg); 640 } else { 641 if (clk->flags & VIRTUAL_IO_ADDRESS) 642 regval32 = __raw_readw(clk->enable_reg); 643 else 644 regval32 = omap_readw(clk->enable_reg); 645 } 646 647 if ((regval32 & (1 << clk->enable_bit)) == 0) 648 return; 649 650 /* FIXME: This clock seems to be necessary but no-one 651 * has asked for its activation. */ 652 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ 653 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ 654 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ 655 ) { 656 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", 657 clk->name); 658 return; 659 } 660 661 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); 662 clk->ops->disable(clk); 663 printk(" done\n"); 664 } 665 666 #else 667 #define omap1_clk_disable_unused NULL 668 #endif 669 670 static struct clk_functions omap1_clk_functions = { 671 .clk_enable = omap1_clk_enable, 672 .clk_disable = omap1_clk_disable, 673 .clk_round_rate = omap1_clk_round_rate, 674 .clk_set_rate = omap1_clk_set_rate, 675 .clk_disable_unused = omap1_clk_disable_unused, 676 }; 677 678 int __init omap1_clk_init(void) 679 { 680 struct clk ** clkp; 681 const struct omap_clock_config *info; 682 int crystal_type = 0; /* Default 12 MHz */ 683 u32 reg; 684 685 #ifdef CONFIG_DEBUG_LL 686 /* Resets some clocks that may be left on from bootloader, 687 * but leaves serial clocks on. 688 */ 689 omap_writel(0x3 << 29, MOD_CONF_CTRL_0); 690 #endif 691 692 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 693 reg = omap_readw(SOFT_REQ_REG) & (1 << 4); 694 omap_writew(reg, SOFT_REQ_REG); 695 if (!cpu_is_omap15xx()) 696 omap_writew(0, SOFT_REQ_REG2); 697 698 clk_init(&omap1_clk_functions); 699 700 /* By default all idlect1 clocks are allowed to idle */ 701 arm_idlect1_mask = ~0; 702 703 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { 704 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { 705 clk_register(*clkp); 706 continue; 707 } 708 709 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { 710 clk_register(*clkp); 711 continue; 712 } 713 714 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { 715 clk_register(*clkp); 716 continue; 717 } 718 719 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { 720 clk_register(*clkp); 721 continue; 722 } 723 } 724 725 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); 726 if (info != NULL) { 727 if (!cpu_is_omap15xx()) 728 crystal_type = info->system_clock_type; 729 } 730 731 #if defined(CONFIG_ARCH_OMAP730) 732 ck_ref.rate = 13000000; 733 #elif defined(CONFIG_ARCH_OMAP16XX) 734 if (crystal_type == 2) 735 ck_ref.rate = 19200000; 736 #endif 737 738 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", 739 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), 740 omap_readw(ARM_CKCTL)); 741 742 /* We want to be in syncronous scalable mode */ 743 omap_writew(0x1000, ARM_SYSST); 744 745 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER 746 /* Use values set by bootloader. Determine PLL rate and recalculate 747 * dependent clocks as if kernel had changed PLL or divisors. 748 */ 749 { 750 unsigned pll_ctl_val = omap_readw(DPLL_CTL); 751 752 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ 753 if (pll_ctl_val & 0x10) { 754 /* PLL enabled, apply multiplier and divisor */ 755 if (pll_ctl_val & 0xf80) 756 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; 757 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; 758 } else { 759 /* PLL disabled, apply bypass divisor */ 760 switch (pll_ctl_val & 0xc) { 761 case 0: 762 break; 763 case 0x4: 764 ck_dpll1.rate /= 2; 765 break; 766 default: 767 ck_dpll1.rate /= 4; 768 break; 769 } 770 } 771 } 772 #else 773 /* Find the highest supported frequency and enable it */ 774 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 775 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 776 /* Guess sane values (60MHz) */ 777 omap_writew(0x2290, DPLL_CTL); 778 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); 779 ck_dpll1.rate = 60000000; 780 } 781 #endif 782 propagate_rate(&ck_dpll1); 783 /* Cache rates for clocks connected to ck_ref (not dpll1) */ 784 propagate_rate(&ck_ref); 785 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " 786 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 787 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, 788 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 789 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 790 791 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) 792 /* Select slicer output as OMAP input clock */ 793 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 794 #endif 795 796 /* Amstrad Delta wants BCLK high when inactive */ 797 if (machine_is_ams_delta()) 798 omap_writel(omap_readl(ULPD_CLOCK_CTRL) | 799 (1 << SDW_MCLK_INV_BIT), 800 ULPD_CLOCK_CTRL); 801 802 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 803 /* (on 730, bit 13 must not be cleared) */ 804 if (cpu_is_omap730()) 805 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 806 else 807 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 808 809 /* Put DSP/MPUI into reset until needed */ 810 omap_writew(0, ARM_RSTCT1); 811 omap_writew(1, ARM_RSTCT2); 812 omap_writew(0x400, ARM_IDLECT1); 813 814 /* 815 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) 816 * of the ARM_IDLECT2 register must be set to zero. The power-on 817 * default value of this bit is one. 818 */ 819 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ 820 821 /* 822 * Only enable those clocks we will need, let the drivers 823 * enable other clocks as necessary 824 */ 825 clk_enable(&armper_ck.clk); 826 clk_enable(&armxor_ck.clk); 827 clk_enable(&armtim_ck.clk); /* This should be done by timer code */ 828 829 if (cpu_is_omap15xx()) 830 clk_enable(&arm_gpio_ck); 831 832 return 0; 833 } 834 835