1 /* 2 * linux/arch/arm/mach-omap1/clock.c 3 * 4 * Copyright (C) 2004 - 2005 Nokia corporation 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 6 * 7 * Modified to use omap shared clock framework by 8 * Tony Lindgren <tony@atomide.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/list.h> 17 #include <linux/errno.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 22 #include <asm/mach-types.h> 23 #include <asm/clkdev.h> 24 25 #include <mach/cpu.h> 26 #include <mach/usb.h> 27 #include <mach/clock.h> 28 #include <mach/sram.h> 29 30 static const struct clkops clkops_generic; 31 static const struct clkops clkops_uart; 32 static const struct clkops clkops_dspck; 33 34 #include "clock.h" 35 36 static int clk_omap1_dummy_enable(struct clk *clk) 37 { 38 return 0; 39 } 40 41 static void clk_omap1_dummy_disable(struct clk *clk) 42 { 43 } 44 45 static const struct clkops clkops_dummy = { 46 .enable = clk_omap1_dummy_enable, 47 .disable = clk_omap1_dummy_disable, 48 }; 49 50 static struct clk dummy_ck = { 51 .name = "dummy", 52 .ops = &clkops_dummy, 53 .flags = RATE_FIXED, 54 }; 55 56 struct omap_clk { 57 u32 cpu; 58 struct clk_lookup lk; 59 }; 60 61 #define CLK(dev, con, ck, cp) \ 62 { \ 63 .cpu = cp, \ 64 .lk = { \ 65 .dev_id = dev, \ 66 .con_id = con, \ 67 .clk = ck, \ 68 }, \ 69 } 70 71 #define CK_310 (1 << 0) 72 #define CK_730 (1 << 1) 73 #define CK_1510 (1 << 2) 74 #define CK_16XX (1 << 3) 75 76 static struct omap_clk omap_clks[] = { 77 /* non-ULPD clocks */ 78 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), 79 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), 80 /* CK_GEN1 clocks */ 81 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), 82 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), 83 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), 84 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 85 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), 86 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), 87 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), 88 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), 89 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), 90 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), 91 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), 92 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), 93 /* CK_GEN2 clocks */ 94 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), 95 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), 96 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), 97 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 98 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), 99 /* CK_GEN3 clocks */ 100 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), 101 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), 102 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), 103 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), 104 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), 105 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), 106 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), 107 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), 108 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), 109 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), 110 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), 111 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), 112 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), 113 /* ULPD clocks */ 114 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), 115 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), 116 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), 117 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), 118 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), 119 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), 120 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), 121 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), 122 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), 123 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), 124 CLK(NULL, "mclk", &mclk_16xx, CK_16XX), 125 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), 126 CLK(NULL, "bclk", &bclk_16xx, CK_16XX), 127 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), 128 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 129 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), 130 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), 131 /* Virtual clocks */ 132 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), 133 CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), 134 CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), 135 CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), 136 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), 137 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), 138 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), 139 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), 140 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), 141 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), 142 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 143 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 144 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 145 }; 146 147 static int omap1_clk_enable_generic(struct clk * clk); 148 static int omap1_clk_enable(struct clk *clk); 149 static void omap1_clk_disable_generic(struct clk * clk); 150 static void omap1_clk_disable(struct clk *clk); 151 152 __u32 arm_idlect1_mask; 153 154 /*------------------------------------------------------------------------- 155 * Omap1 specific clock functions 156 *-------------------------------------------------------------------------*/ 157 158 static void omap1_watchdog_recalc(struct clk * clk) 159 { 160 clk->rate = clk->parent->rate / 14; 161 } 162 163 static void omap1_uart_recalc(struct clk * clk) 164 { 165 unsigned int val = omap_readl(clk->enable_reg); 166 if (val & clk->enable_bit) 167 clk->rate = 48000000; 168 else 169 clk->rate = 12000000; 170 } 171 172 static void omap1_sossi_recalc(struct clk *clk) 173 { 174 u32 div = omap_readl(MOD_CONF_CTRL_1); 175 176 div = (div >> 17) & 0x7; 177 div++; 178 clk->rate = clk->parent->rate / div; 179 } 180 181 static int omap1_clk_enable_dsp_domain(struct clk *clk) 182 { 183 int retval; 184 185 retval = omap1_clk_enable(&api_ck.clk); 186 if (!retval) { 187 retval = omap1_clk_enable_generic(clk); 188 omap1_clk_disable(&api_ck.clk); 189 } 190 191 return retval; 192 } 193 194 static void omap1_clk_disable_dsp_domain(struct clk *clk) 195 { 196 if (omap1_clk_enable(&api_ck.clk) == 0) { 197 omap1_clk_disable_generic(clk); 198 omap1_clk_disable(&api_ck.clk); 199 } 200 } 201 202 static const struct clkops clkops_dspck = { 203 .enable = &omap1_clk_enable_dsp_domain, 204 .disable = &omap1_clk_disable_dsp_domain, 205 }; 206 207 static int omap1_clk_enable_uart_functional(struct clk *clk) 208 { 209 int ret; 210 struct uart_clk *uclk; 211 212 ret = omap1_clk_enable_generic(clk); 213 if (ret == 0) { 214 /* Set smart idle acknowledgement mode */ 215 uclk = (struct uart_clk *)clk; 216 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, 217 uclk->sysc_addr); 218 } 219 220 return ret; 221 } 222 223 static void omap1_clk_disable_uart_functional(struct clk *clk) 224 { 225 struct uart_clk *uclk; 226 227 /* Set force idle acknowledgement mode */ 228 uclk = (struct uart_clk *)clk; 229 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); 230 231 omap1_clk_disable_generic(clk); 232 } 233 234 static const struct clkops clkops_uart = { 235 .enable = &omap1_clk_enable_uart_functional, 236 .disable = &omap1_clk_disable_uart_functional, 237 }; 238 239 static void omap1_clk_allow_idle(struct clk *clk) 240 { 241 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 242 243 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 244 return; 245 246 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) 247 arm_idlect1_mask |= 1 << iclk->idlect_shift; 248 } 249 250 static void omap1_clk_deny_idle(struct clk *clk) 251 { 252 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 253 254 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 255 return; 256 257 if (iclk->no_idle_count++ == 0) 258 arm_idlect1_mask &= ~(1 << iclk->idlect_shift); 259 } 260 261 static __u16 verify_ckctl_value(__u16 newval) 262 { 263 /* This function checks for following limitations set 264 * by the hardware (all conditions must be true): 265 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 266 * ARM_CK >= TC_CK 267 * DSP_CK >= TC_CK 268 * DSPMMU_CK >= TC_CK 269 * 270 * In addition following rules are enforced: 271 * LCD_CK <= TC_CK 272 * ARMPER_CK <= TC_CK 273 * 274 * However, maximum frequencies are not checked for! 275 */ 276 __u8 per_exp; 277 __u8 lcd_exp; 278 __u8 arm_exp; 279 __u8 dsp_exp; 280 __u8 tc_exp; 281 __u8 dspmmu_exp; 282 283 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; 284 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; 285 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; 286 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; 287 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; 288 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; 289 290 if (dspmmu_exp < dsp_exp) 291 dspmmu_exp = dsp_exp; 292 if (dspmmu_exp > dsp_exp+1) 293 dspmmu_exp = dsp_exp+1; 294 if (tc_exp < arm_exp) 295 tc_exp = arm_exp; 296 if (tc_exp < dspmmu_exp) 297 tc_exp = dspmmu_exp; 298 if (tc_exp > lcd_exp) 299 lcd_exp = tc_exp; 300 if (tc_exp > per_exp) 301 per_exp = tc_exp; 302 303 newval &= 0xf000; 304 newval |= per_exp << CKCTL_PERDIV_OFFSET; 305 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; 306 newval |= arm_exp << CKCTL_ARMDIV_OFFSET; 307 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; 308 newval |= tc_exp << CKCTL_TCDIV_OFFSET; 309 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; 310 311 return newval; 312 } 313 314 static int calc_dsor_exp(struct clk *clk, unsigned long rate) 315 { 316 /* Note: If target frequency is too low, this function will return 4, 317 * which is invalid value. Caller must check for this value and act 318 * accordingly. 319 * 320 * Note: This function does not check for following limitations set 321 * by the hardware (all conditions must be true): 322 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 323 * ARM_CK >= TC_CK 324 * DSP_CK >= TC_CK 325 * DSPMMU_CK >= TC_CK 326 */ 327 unsigned long realrate; 328 struct clk * parent; 329 unsigned dsor_exp; 330 331 parent = clk->parent; 332 if (unlikely(parent == NULL)) 333 return -EIO; 334 335 realrate = parent->rate; 336 for (dsor_exp=0; dsor_exp<4; dsor_exp++) { 337 if (realrate <= rate) 338 break; 339 340 realrate /= 2; 341 } 342 343 return dsor_exp; 344 } 345 346 static void omap1_ckctl_recalc(struct clk * clk) 347 { 348 int dsor; 349 350 /* Calculate divisor encoded as 2-bit exponent */ 351 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 352 353 if (unlikely(clk->rate == clk->parent->rate / dsor)) 354 return; /* No change, quick exit */ 355 clk->rate = clk->parent->rate / dsor; 356 } 357 358 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) 359 { 360 int dsor; 361 362 /* Calculate divisor encoded as 2-bit exponent 363 * 364 * The clock control bits are in DSP domain, 365 * so api_ck is needed for access. 366 * Note that DSP_CKCTL virt addr = phys addr, so 367 * we must use __raw_readw() instead of omap_readw(). 368 */ 369 omap1_clk_enable(&api_ck.clk); 370 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); 371 omap1_clk_disable(&api_ck.clk); 372 373 if (unlikely(clk->rate == clk->parent->rate / dsor)) 374 return; /* No change, quick exit */ 375 clk->rate = clk->parent->rate / dsor; 376 } 377 378 /* MPU virtual clock functions */ 379 static int omap1_select_table_rate(struct clk * clk, unsigned long rate) 380 { 381 /* Find the highest supported frequency <= rate and switch to it */ 382 struct mpu_rate * ptr; 383 384 if (clk != &virtual_ck_mpu) 385 return -EINVAL; 386 387 for (ptr = rate_table; ptr->rate; ptr++) { 388 if (ptr->xtal != ck_ref.rate) 389 continue; 390 391 /* DPLL1 cannot be reprogrammed without risking system crash */ 392 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) 393 continue; 394 395 /* Can check only after xtal frequency check */ 396 if (ptr->rate <= rate) 397 break; 398 } 399 400 if (!ptr->rate) 401 return -EINVAL; 402 403 /* 404 * In most cases we should not need to reprogram DPLL. 405 * Reprogramming the DPLL is tricky, it must be done from SRAM. 406 * (on 730, bit 13 must always be 1) 407 */ 408 if (cpu_is_omap730()) 409 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); 410 else 411 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 412 413 ck_dpll1.rate = ptr->pll_rate; 414 return 0; 415 } 416 417 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) 418 { 419 int dsor_exp; 420 u16 regval; 421 422 dsor_exp = calc_dsor_exp(clk, rate); 423 if (dsor_exp > 3) 424 dsor_exp = -EINVAL; 425 if (dsor_exp < 0) 426 return dsor_exp; 427 428 regval = __raw_readw(DSP_CKCTL); 429 regval &= ~(3 << clk->rate_offset); 430 regval |= dsor_exp << clk->rate_offset; 431 __raw_writew(regval, DSP_CKCTL); 432 clk->rate = clk->parent->rate / (1 << dsor_exp); 433 434 return 0; 435 } 436 437 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) 438 { 439 int dsor_exp = calc_dsor_exp(clk, rate); 440 if (dsor_exp < 0) 441 return dsor_exp; 442 if (dsor_exp > 3) 443 dsor_exp = 3; 444 return clk->parent->rate / (1 << dsor_exp); 445 } 446 447 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) 448 { 449 int dsor_exp; 450 u16 regval; 451 452 dsor_exp = calc_dsor_exp(clk, rate); 453 if (dsor_exp > 3) 454 dsor_exp = -EINVAL; 455 if (dsor_exp < 0) 456 return dsor_exp; 457 458 regval = omap_readw(ARM_CKCTL); 459 regval &= ~(3 << clk->rate_offset); 460 regval |= dsor_exp << clk->rate_offset; 461 regval = verify_ckctl_value(regval); 462 omap_writew(regval, ARM_CKCTL); 463 clk->rate = clk->parent->rate / (1 << dsor_exp); 464 return 0; 465 } 466 467 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) 468 { 469 /* Find the highest supported frequency <= rate */ 470 struct mpu_rate * ptr; 471 long highest_rate; 472 473 if (clk != &virtual_ck_mpu) 474 return -EINVAL; 475 476 highest_rate = -EINVAL; 477 478 for (ptr = rate_table; ptr->rate; ptr++) { 479 if (ptr->xtal != ck_ref.rate) 480 continue; 481 482 highest_rate = ptr->rate; 483 484 /* Can check only after xtal frequency check */ 485 if (ptr->rate <= rate) 486 break; 487 } 488 489 return highest_rate; 490 } 491 492 static unsigned calc_ext_dsor(unsigned long rate) 493 { 494 unsigned dsor; 495 496 /* MCLK and BCLK divisor selection is not linear: 497 * freq = 96MHz / dsor 498 * 499 * RATIO_SEL range: dsor <-> RATIO_SEL 500 * 0..6: (RATIO_SEL+2) <-> (dsor-2) 501 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) 502 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 503 * can not be used. 504 */ 505 for (dsor = 2; dsor < 96; ++dsor) { 506 if ((dsor & 1) && dsor > 8) 507 continue; 508 if (rate >= 96000000 / dsor) 509 break; 510 } 511 return dsor; 512 } 513 514 /* Only needed on 1510 */ 515 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) 516 { 517 unsigned int val; 518 519 val = omap_readl(clk->enable_reg); 520 if (rate == 12000000) 521 val &= ~(1 << clk->enable_bit); 522 else if (rate == 48000000) 523 val |= (1 << clk->enable_bit); 524 else 525 return -EINVAL; 526 omap_writel(val, clk->enable_reg); 527 clk->rate = rate; 528 529 return 0; 530 } 531 532 /* External clock (MCLK & BCLK) functions */ 533 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) 534 { 535 unsigned dsor; 536 __u16 ratio_bits; 537 538 dsor = calc_ext_dsor(rate); 539 clk->rate = 96000000 / dsor; 540 if (dsor > 8) 541 ratio_bits = ((dsor - 8) / 2 + 6) << 2; 542 else 543 ratio_bits = (dsor - 2) << 2; 544 545 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; 546 omap_writew(ratio_bits, clk->enable_reg); 547 548 return 0; 549 } 550 551 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) 552 { 553 u32 l; 554 int div; 555 unsigned long p_rate; 556 557 p_rate = clk->parent->rate; 558 /* Round towards slower frequency */ 559 div = (p_rate + rate - 1) / rate; 560 div--; 561 if (div < 0 || div > 7) 562 return -EINVAL; 563 564 l = omap_readl(MOD_CONF_CTRL_1); 565 l &= ~(7 << 17); 566 l |= div << 17; 567 omap_writel(l, MOD_CONF_CTRL_1); 568 569 clk->rate = p_rate / (div + 1); 570 571 return 0; 572 } 573 574 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) 575 { 576 return 96000000 / calc_ext_dsor(rate); 577 } 578 579 static void omap1_init_ext_clk(struct clk * clk) 580 { 581 unsigned dsor; 582 __u16 ratio_bits; 583 584 /* Determine current rate and ensure clock is based on 96MHz APLL */ 585 ratio_bits = omap_readw(clk->enable_reg) & ~1; 586 omap_writew(ratio_bits, clk->enable_reg); 587 588 ratio_bits = (ratio_bits & 0xfc) >> 2; 589 if (ratio_bits > 6) 590 dsor = (ratio_bits - 6) * 2 + 8; 591 else 592 dsor = ratio_bits + 2; 593 594 clk-> rate = 96000000 / dsor; 595 } 596 597 static int omap1_clk_enable(struct clk *clk) 598 { 599 int ret = 0; 600 if (clk->usecount++ == 0) { 601 if (likely(clk->parent)) { 602 ret = omap1_clk_enable(clk->parent); 603 604 if (unlikely(ret != 0)) { 605 clk->usecount--; 606 return ret; 607 } 608 609 if (clk->flags & CLOCK_NO_IDLE_PARENT) 610 omap1_clk_deny_idle(clk->parent); 611 } 612 613 ret = clk->ops->enable(clk); 614 615 if (unlikely(ret != 0) && clk->parent) { 616 omap1_clk_disable(clk->parent); 617 clk->usecount--; 618 } 619 } 620 621 return ret; 622 } 623 624 static void omap1_clk_disable(struct clk *clk) 625 { 626 if (clk->usecount > 0 && !(--clk->usecount)) { 627 clk->ops->disable(clk); 628 if (likely(clk->parent)) { 629 omap1_clk_disable(clk->parent); 630 if (clk->flags & CLOCK_NO_IDLE_PARENT) 631 omap1_clk_allow_idle(clk->parent); 632 } 633 } 634 } 635 636 static int omap1_clk_enable_generic(struct clk *clk) 637 { 638 __u16 regval16; 639 __u32 regval32; 640 641 if (unlikely(clk->enable_reg == NULL)) { 642 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 643 clk->name); 644 return -EINVAL; 645 } 646 647 if (clk->flags & ENABLE_REG_32BIT) { 648 if (clk->flags & VIRTUAL_IO_ADDRESS) { 649 regval32 = __raw_readl(clk->enable_reg); 650 regval32 |= (1 << clk->enable_bit); 651 __raw_writel(regval32, clk->enable_reg); 652 } else { 653 regval32 = omap_readl(clk->enable_reg); 654 regval32 |= (1 << clk->enable_bit); 655 omap_writel(regval32, clk->enable_reg); 656 } 657 } else { 658 if (clk->flags & VIRTUAL_IO_ADDRESS) { 659 regval16 = __raw_readw(clk->enable_reg); 660 regval16 |= (1 << clk->enable_bit); 661 __raw_writew(regval16, clk->enable_reg); 662 } else { 663 regval16 = omap_readw(clk->enable_reg); 664 regval16 |= (1 << clk->enable_bit); 665 omap_writew(regval16, clk->enable_reg); 666 } 667 } 668 669 return 0; 670 } 671 672 static void omap1_clk_disable_generic(struct clk *clk) 673 { 674 __u16 regval16; 675 __u32 regval32; 676 677 if (clk->enable_reg == NULL) 678 return; 679 680 if (clk->flags & ENABLE_REG_32BIT) { 681 if (clk->flags & VIRTUAL_IO_ADDRESS) { 682 regval32 = __raw_readl(clk->enable_reg); 683 regval32 &= ~(1 << clk->enable_bit); 684 __raw_writel(regval32, clk->enable_reg); 685 } else { 686 regval32 = omap_readl(clk->enable_reg); 687 regval32 &= ~(1 << clk->enable_bit); 688 omap_writel(regval32, clk->enable_reg); 689 } 690 } else { 691 if (clk->flags & VIRTUAL_IO_ADDRESS) { 692 regval16 = __raw_readw(clk->enable_reg); 693 regval16 &= ~(1 << clk->enable_bit); 694 __raw_writew(regval16, clk->enable_reg); 695 } else { 696 regval16 = omap_readw(clk->enable_reg); 697 regval16 &= ~(1 << clk->enable_bit); 698 omap_writew(regval16, clk->enable_reg); 699 } 700 } 701 } 702 703 static const struct clkops clkops_generic = { 704 .enable = &omap1_clk_enable_generic, 705 .disable = &omap1_clk_disable_generic, 706 }; 707 708 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 709 { 710 if (clk->flags & RATE_FIXED) 711 return clk->rate; 712 713 if (clk->round_rate != NULL) 714 return clk->round_rate(clk, rate); 715 716 return clk->rate; 717 } 718 719 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) 720 { 721 int ret = -EINVAL; 722 723 if (clk->set_rate) 724 ret = clk->set_rate(clk, rate); 725 return ret; 726 } 727 728 /*------------------------------------------------------------------------- 729 * Omap1 clock reset and init functions 730 *-------------------------------------------------------------------------*/ 731 732 #ifdef CONFIG_OMAP_RESET_CLOCKS 733 734 static void __init omap1_clk_disable_unused(struct clk *clk) 735 { 736 __u32 regval32; 737 738 /* Clocks in the DSP domain need api_ck. Just assume bootloader 739 * has not enabled any DSP clocks */ 740 if (clk->enable_reg == DSP_IDLECT2) { 741 printk(KERN_INFO "Skipping reset check for DSP domain " 742 "clock \"%s\"\n", clk->name); 743 return; 744 } 745 746 /* Is the clock already disabled? */ 747 if (clk->flags & ENABLE_REG_32BIT) { 748 if (clk->flags & VIRTUAL_IO_ADDRESS) 749 regval32 = __raw_readl(clk->enable_reg); 750 else 751 regval32 = omap_readl(clk->enable_reg); 752 } else { 753 if (clk->flags & VIRTUAL_IO_ADDRESS) 754 regval32 = __raw_readw(clk->enable_reg); 755 else 756 regval32 = omap_readw(clk->enable_reg); 757 } 758 759 if ((regval32 & (1 << clk->enable_bit)) == 0) 760 return; 761 762 /* FIXME: This clock seems to be necessary but no-one 763 * has asked for its activation. */ 764 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ 765 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ 766 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ 767 ) { 768 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", 769 clk->name); 770 return; 771 } 772 773 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); 774 clk->ops->disable(clk); 775 printk(" done\n"); 776 } 777 778 #else 779 #define omap1_clk_disable_unused NULL 780 #endif 781 782 static struct clk_functions omap1_clk_functions = { 783 .clk_enable = omap1_clk_enable, 784 .clk_disable = omap1_clk_disable, 785 .clk_round_rate = omap1_clk_round_rate, 786 .clk_set_rate = omap1_clk_set_rate, 787 .clk_disable_unused = omap1_clk_disable_unused, 788 }; 789 790 int __init omap1_clk_init(void) 791 { 792 struct omap_clk *c; 793 const struct omap_clock_config *info; 794 int crystal_type = 0; /* Default 12 MHz */ 795 u32 reg, cpu_mask; 796 797 #ifdef CONFIG_DEBUG_LL 798 /* Resets some clocks that may be left on from bootloader, 799 * but leaves serial clocks on. 800 */ 801 omap_writel(0x3 << 29, MOD_CONF_CTRL_0); 802 #endif 803 804 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 805 reg = omap_readw(SOFT_REQ_REG) & (1 << 4); 806 omap_writew(reg, SOFT_REQ_REG); 807 if (!cpu_is_omap15xx()) 808 omap_writew(0, SOFT_REQ_REG2); 809 810 clk_init(&omap1_clk_functions); 811 812 /* By default all idlect1 clocks are allowed to idle */ 813 arm_idlect1_mask = ~0; 814 815 cpu_mask = 0; 816 if (cpu_is_omap16xx()) 817 cpu_mask |= CK_16XX; 818 if (cpu_is_omap1510()) 819 cpu_mask |= CK_1510; 820 if (cpu_is_omap730()) 821 cpu_mask |= CK_730; 822 if (cpu_is_omap310()) 823 cpu_mask |= CK_310; 824 825 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 826 if (c->cpu & cpu_mask) { 827 clkdev_add(&c->lk); 828 clk_register(c->lk.clk); 829 } 830 831 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); 832 if (info != NULL) { 833 if (!cpu_is_omap15xx()) 834 crystal_type = info->system_clock_type; 835 } 836 837 #if defined(CONFIG_ARCH_OMAP730) 838 ck_ref.rate = 13000000; 839 #elif defined(CONFIG_ARCH_OMAP16XX) 840 if (crystal_type == 2) 841 ck_ref.rate = 19200000; 842 #endif 843 844 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", 845 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), 846 omap_readw(ARM_CKCTL)); 847 848 /* We want to be in syncronous scalable mode */ 849 omap_writew(0x1000, ARM_SYSST); 850 851 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER 852 /* Use values set by bootloader. Determine PLL rate and recalculate 853 * dependent clocks as if kernel had changed PLL or divisors. 854 */ 855 { 856 unsigned pll_ctl_val = omap_readw(DPLL_CTL); 857 858 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ 859 if (pll_ctl_val & 0x10) { 860 /* PLL enabled, apply multiplier and divisor */ 861 if (pll_ctl_val & 0xf80) 862 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; 863 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; 864 } else { 865 /* PLL disabled, apply bypass divisor */ 866 switch (pll_ctl_val & 0xc) { 867 case 0: 868 break; 869 case 0x4: 870 ck_dpll1.rate /= 2; 871 break; 872 default: 873 ck_dpll1.rate /= 4; 874 break; 875 } 876 } 877 } 878 #else 879 /* Find the highest supported frequency and enable it */ 880 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 881 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 882 /* Guess sane values (60MHz) */ 883 omap_writew(0x2290, DPLL_CTL); 884 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); 885 ck_dpll1.rate = 60000000; 886 } 887 #endif 888 propagate_rate(&ck_dpll1); 889 /* Cache rates for clocks connected to ck_ref (not dpll1) */ 890 propagate_rate(&ck_ref); 891 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " 892 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 893 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, 894 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 895 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 896 897 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) 898 /* Select slicer output as OMAP input clock */ 899 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 900 #endif 901 902 /* Amstrad Delta wants BCLK high when inactive */ 903 if (machine_is_ams_delta()) 904 omap_writel(omap_readl(ULPD_CLOCK_CTRL) | 905 (1 << SDW_MCLK_INV_BIT), 906 ULPD_CLOCK_CTRL); 907 908 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 909 /* (on 730, bit 13 must not be cleared) */ 910 if (cpu_is_omap730()) 911 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 912 else 913 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 914 915 /* Put DSP/MPUI into reset until needed */ 916 omap_writew(0, ARM_RSTCT1); 917 omap_writew(1, ARM_RSTCT2); 918 omap_writew(0x400, ARM_IDLECT1); 919 920 /* 921 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) 922 * of the ARM_IDLECT2 register must be set to zero. The power-on 923 * default value of this bit is one. 924 */ 925 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ 926 927 /* 928 * Only enable those clocks we will need, let the drivers 929 * enable other clocks as necessary 930 */ 931 clk_enable(&armper_ck.clk); 932 clk_enable(&armxor_ck.clk); 933 clk_enable(&armtim_ck.clk); /* This should be done by timer code */ 934 935 if (cpu_is_omap15xx()) 936 clk_enable(&arm_gpio_ck); 937 938 return 0; 939 } 940