1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Copyright 2012 Linaro Ltd. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk/mxs.h> 9 #include <linux/clkdev.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/gpio.h> 13 #include <linux/init.h> 14 #include <linux/irqchip/mxs.h> 15 #include <linux/reboot.h> 16 #include <linux/micrel_phy.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/phy.h> 20 #include <linux/sys_soc.h> 21 #include <asm/mach/arch.h> 22 #include <asm/mach/map.h> 23 #include <asm/mach/time.h> 24 #include <asm/system_info.h> 25 #include <asm/system_misc.h> 26 27 #include "pm.h" 28 29 /* MXS DIGCTL SAIF CLKMUX */ 30 #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 31 #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 32 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 33 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 34 35 #define HW_DIGCTL_CHIPID 0x310 36 #define HW_DIGCTL_CHIPID_MASK (0xffff << 16) 37 #define HW_DIGCTL_REV_MASK 0xff 38 #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) 39 #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) 40 41 #define MXS_CHIP_REVISION_1_0 0x10 42 #define MXS_CHIP_REVISION_1_1 0x11 43 #define MXS_CHIP_REVISION_1_2 0x12 44 #define MXS_CHIP_REVISION_1_3 0x13 45 #define MXS_CHIP_REVISION_1_4 0x14 46 #define MXS_CHIP_REV_UNKNOWN 0xff 47 48 #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) 49 50 #define MXS_SET_ADDR 0x4 51 #define MXS_CLR_ADDR 0x8 52 #define MXS_TOG_ADDR 0xc 53 54 #define HW_OCOTP_OPS2 19 /* offset 0x150 */ 55 #define HW_OCOTP_OPS3 20 /* offset 0x160 */ 56 57 static u32 chipid; 58 static u32 socid; 59 60 static void __iomem *reset_addr; 61 62 static inline void __mxs_setl(u32 mask, void __iomem *reg) 63 { 64 __raw_writel(mask, reg + MXS_SET_ADDR); 65 } 66 67 static inline void __mxs_clrl(u32 mask, void __iomem *reg) 68 { 69 __raw_writel(mask, reg + MXS_CLR_ADDR); 70 } 71 72 static inline void __mxs_togl(u32 mask, void __iomem *reg) 73 { 74 __raw_writel(mask, reg + MXS_TOG_ADDR); 75 } 76 77 #define OCOTP_WORD_OFFSET 0x20 78 #define OCOTP_WORD_COUNT 0x20 79 80 #define BM_OCOTP_CTRL_BUSY (1 << 8) 81 #define BM_OCOTP_CTRL_ERROR (1 << 9) 82 #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) 83 84 static DEFINE_MUTEX(ocotp_mutex); 85 static u32 ocotp_words[OCOTP_WORD_COUNT]; 86 87 static const u32 *mxs_get_ocotp(void) 88 { 89 struct device_node *np; 90 void __iomem *ocotp_base; 91 int timeout = 0x400; 92 size_t i; 93 static int once; 94 95 if (once) 96 return ocotp_words; 97 98 np = of_find_compatible_node(NULL, NULL, "fsl,ocotp"); 99 ocotp_base = of_iomap(np, 0); 100 WARN_ON(!ocotp_base); 101 102 mutex_lock(&ocotp_mutex); 103 104 /* 105 * clk_enable(hbus_clk) for ocotp can be skipped 106 * as it must be on when system is running. 107 */ 108 109 /* try to clear ERROR bit */ 110 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); 111 112 /* check both BUSY and ERROR cleared */ 113 while ((__raw_readl(ocotp_base) & 114 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) 115 cpu_relax(); 116 117 if (unlikely(!timeout)) 118 goto error_unlock; 119 120 /* open OCOTP banks for read */ 121 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); 122 123 /* approximately wait 32 hclk cycles */ 124 udelay(1); 125 126 /* poll BUSY bit becoming cleared */ 127 timeout = 0x400; 128 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) 129 cpu_relax(); 130 131 if (unlikely(!timeout)) 132 goto error_unlock; 133 134 for (i = 0; i < OCOTP_WORD_COUNT; i++) 135 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + 136 i * 0x10); 137 138 /* close banks for power saving */ 139 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); 140 141 once = 1; 142 143 mutex_unlock(&ocotp_mutex); 144 145 return ocotp_words; 146 147 error_unlock: 148 mutex_unlock(&ocotp_mutex); 149 pr_err("%s: timeout in reading OCOTP\n", __func__); 150 return NULL; 151 } 152 153 enum mac_oui { 154 OUI_FSL, 155 OUI_DENX, 156 OUI_CRYSTALFONTZ, 157 OUI_I2SE, 158 OUI_ARMADEUS, 159 }; 160 161 static void __init update_fec_mac_prop(enum mac_oui oui) 162 { 163 struct device_node *np, *from = NULL; 164 struct property *newmac; 165 const u32 *ocotp = mxs_get_ocotp(); 166 u8 *macaddr; 167 u32 val; 168 int i; 169 170 for (i = 0; i < 2; i++) { 171 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); 172 if (!np) 173 return; 174 175 from = np; 176 177 if (of_property_present(np, "local-mac-address")) 178 continue; 179 180 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); 181 if (!newmac) 182 return; 183 newmac->value = newmac + 1; 184 newmac->length = 6; 185 186 newmac->name = kstrdup("local-mac-address", GFP_KERNEL); 187 if (!newmac->name) { 188 kfree(newmac); 189 return; 190 } 191 192 /* 193 * OCOTP only stores the last 4 octets for each mac address, 194 * so hard-code OUI here. 195 */ 196 macaddr = newmac->value; 197 switch (oui) { 198 case OUI_FSL: 199 macaddr[0] = 0x00; 200 macaddr[1] = 0x04; 201 macaddr[2] = 0x9f; 202 break; 203 case OUI_DENX: 204 macaddr[0] = 0xc0; 205 macaddr[1] = 0xe5; 206 macaddr[2] = 0x4e; 207 break; 208 case OUI_CRYSTALFONTZ: 209 macaddr[0] = 0x58; 210 macaddr[1] = 0xb9; 211 macaddr[2] = 0xe1; 212 break; 213 case OUI_I2SE: 214 macaddr[0] = 0x00; 215 macaddr[1] = 0x01; 216 macaddr[2] = 0x87; 217 break; 218 case OUI_ARMADEUS: 219 macaddr[0] = 0x00; 220 macaddr[1] = 0x1e; 221 macaddr[2] = 0xac; 222 break; 223 } 224 val = ocotp[i]; 225 macaddr[3] = (val >> 16) & 0xff; 226 macaddr[4] = (val >> 8) & 0xff; 227 macaddr[5] = (val >> 0) & 0xff; 228 229 of_update_property(np, newmac); 230 } 231 } 232 233 static inline void enable_clk_enet_out(void) 234 { 235 struct clk *clk = clk_get_sys("enet_out", NULL); 236 237 if (!IS_ERR(clk)) 238 clk_prepare_enable(clk); 239 } 240 241 static void __init imx28_evk_init(void) 242 { 243 update_fec_mac_prop(OUI_FSL); 244 245 mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); 246 } 247 248 static void __init imx28_apf28_init(void) 249 { 250 update_fec_mac_prop(OUI_ARMADEUS); 251 } 252 253 static int apx4devkit_phy_fixup(struct phy_device *phy) 254 { 255 phy->dev_flags |= MICREL_PHY_50MHZ_CLK; 256 return 0; 257 } 258 259 static void __init apx4devkit_init(void) 260 { 261 enable_clk_enet_out(); 262 263 if (IS_BUILTIN(CONFIG_PHYLIB)) 264 phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK, 265 apx4devkit_phy_fixup); 266 } 267 268 static void __init crystalfontz_init(void) 269 { 270 update_fec_mac_prop(OUI_CRYSTALFONTZ); 271 } 272 273 static void __init duckbill_init(void) 274 { 275 update_fec_mac_prop(OUI_I2SE); 276 } 277 278 static void __init m28cu3_init(void) 279 { 280 update_fec_mac_prop(OUI_DENX); 281 } 282 283 static const char __init *mxs_get_soc_id(void) 284 { 285 struct device_node *np; 286 void __iomem *digctl_base; 287 288 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); 289 digctl_base = of_iomap(np, 0); 290 WARN_ON(!digctl_base); 291 292 chipid = readl(digctl_base + HW_DIGCTL_CHIPID); 293 socid = chipid & HW_DIGCTL_CHIPID_MASK; 294 295 iounmap(digctl_base); 296 of_node_put(np); 297 298 switch (socid) { 299 case HW_DIGCTL_CHIPID_MX23: 300 return "i.MX23"; 301 case HW_DIGCTL_CHIPID_MX28: 302 return "i.MX28"; 303 default: 304 return "Unknown"; 305 } 306 } 307 308 static u32 __init mxs_get_cpu_rev(void) 309 { 310 u32 rev = chipid & HW_DIGCTL_REV_MASK; 311 312 switch (socid) { 313 case HW_DIGCTL_CHIPID_MX23: 314 switch (rev) { 315 case 0x0: 316 return MXS_CHIP_REVISION_1_0; 317 case 0x1: 318 return MXS_CHIP_REVISION_1_1; 319 case 0x2: 320 return MXS_CHIP_REVISION_1_2; 321 case 0x3: 322 return MXS_CHIP_REVISION_1_3; 323 case 0x4: 324 return MXS_CHIP_REVISION_1_4; 325 default: 326 return MXS_CHIP_REV_UNKNOWN; 327 } 328 case HW_DIGCTL_CHIPID_MX28: 329 switch (rev) { 330 case 0x0: 331 return MXS_CHIP_REVISION_1_1; 332 case 0x1: 333 return MXS_CHIP_REVISION_1_2; 334 default: 335 return MXS_CHIP_REV_UNKNOWN; 336 } 337 default: 338 return MXS_CHIP_REV_UNKNOWN; 339 } 340 } 341 342 static const char __init *mxs_get_revision(void) 343 { 344 u32 rev = mxs_get_cpu_rev(); 345 346 if (rev != MXS_CHIP_REV_UNKNOWN) 347 return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf, 348 rev & 0xf); 349 else 350 return kasprintf(GFP_KERNEL, "%s", "Unknown"); 351 } 352 353 #define MX23_CLKCTRL_RESET_OFFSET 0x120 354 #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 355 356 static int __init mxs_restart_init(void) 357 { 358 struct device_node *np; 359 360 np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); 361 reset_addr = of_iomap(np, 0); 362 if (!reset_addr) 363 return -ENODEV; 364 365 if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) 366 reset_addr += MX23_CLKCTRL_RESET_OFFSET; 367 else 368 reset_addr += MX28_CLKCTRL_RESET_OFFSET; 369 of_node_put(np); 370 371 return 0; 372 } 373 374 static void __init eukrea_mbmx283lc_init(void) 375 { 376 mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); 377 } 378 379 static void __init mxs_machine_init(void) 380 { 381 struct device_node *root; 382 struct device *parent; 383 struct soc_device *soc_dev; 384 struct soc_device_attribute *soc_dev_attr; 385 u64 soc_uid = 0; 386 const u32 *ocotp = mxs_get_ocotp(); 387 int ret; 388 389 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 390 if (!soc_dev_attr) 391 return; 392 393 root = of_find_node_by_path("/"); 394 ret = of_property_read_string(root, "model", &soc_dev_attr->machine); 395 if (ret) { 396 kfree(soc_dev_attr); 397 return; 398 } 399 400 soc_dev_attr->family = "Freescale MXS Family"; 401 soc_dev_attr->soc_id = mxs_get_soc_id(); 402 soc_dev_attr->revision = mxs_get_revision(); 403 404 if (socid == HW_DIGCTL_CHIPID_MX23) { 405 soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3]; 406 } else if (socid == HW_DIGCTL_CHIPID_MX28) { 407 soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2]; 408 soc_uid <<= 32; 409 system_serial_low = ocotp[HW_OCOTP_OPS3]; 410 soc_uid |= system_serial_low; 411 } 412 413 if (soc_uid) 414 soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); 415 416 soc_dev = soc_device_register(soc_dev_attr); 417 if (IS_ERR(soc_dev)) { 418 kfree(soc_dev_attr->serial_number); 419 kfree(soc_dev_attr->revision); 420 kfree(soc_dev_attr); 421 return; 422 } 423 424 parent = soc_device_to_device(soc_dev); 425 426 if (of_machine_is_compatible("fsl,imx28-evk")) 427 imx28_evk_init(); 428 if (of_machine_is_compatible("armadeus,imx28-apf28")) 429 imx28_apf28_init(); 430 else if (of_machine_is_compatible("bluegiga,apx4devkit")) 431 apx4devkit_init(); 432 else if (of_machine_is_compatible("crystalfontz,cfa10036")) 433 crystalfontz_init(); 434 else if (of_machine_is_compatible("eukrea,mbmx283lc")) 435 eukrea_mbmx283lc_init(); 436 else if (of_machine_is_compatible("i2se,duckbill") || 437 of_machine_is_compatible("i2se,duckbill-2")) 438 duckbill_init(); 439 else if (of_machine_is_compatible("msr,m28cu3")) 440 m28cu3_init(); 441 442 of_platform_default_populate(NULL, NULL, parent); 443 444 mxs_restart_init(); 445 } 446 447 #define MXS_CLKCTRL_RESET_CHIP (1 << 1) 448 449 /* 450 * Reset the system. It is called by machine_restart(). 451 */ 452 static void mxs_restart(enum reboot_mode mode, const char *cmd) 453 { 454 if (reset_addr) { 455 /* reset the chip */ 456 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); 457 458 pr_err("Failed to assert the chip reset\n"); 459 460 /* Delay to allow the serial port to show the message */ 461 mdelay(50); 462 } 463 464 /* We'll take a jump through zero as a poor second */ 465 soft_restart(0); 466 } 467 468 static const char *const mxs_dt_compat[] __initconst = { 469 "fsl,imx28", 470 "fsl,imx23", 471 NULL, 472 }; 473 474 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") 475 .handle_irq = icoll_handle_irq, 476 .init_machine = mxs_machine_init, 477 .init_late = mxs_pm_init, 478 .dt_compat = mxs_dt_compat, 479 .restart = mxs_restart, 480 MACHINE_END 481