1/* 2 * Copyright (C) 2014 Marvell 3 * 4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 5 * Gregory Clement <gregory.clement@free-electrons.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/linkage.h> 13#include <asm/assembler.h> 14 15 16ENTRY(armada_38x_scu_power_up) 17 mrc p15, 4, r1, c15, c0 @ get SCU base address 18 orr r1, r1, #0x8 @ SCU CPU Power Status Register 19 mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID 20 and r0, r0, #15 21 add r1, r1, r0 22 mov r0, #0x0 23 strb r0, [r1] @ switch SCU power state to Normal mode 24 ret lr 25ENDPROC(armada_38x_scu_power_up) 26 27/* 28 * This is the entry point through which CPUs exiting cpuidle deep 29 * idle state are going. 30 */ 31ENTRY(armada_370_xp_cpu_resume) 32ARM_BE8(setend be ) @ go BE8 if entered LE 33 bl ll_add_cpu_to_smp_group 34 bl ll_enable_coherency 35 b cpu_resume 36ENDPROC(armada_370_xp_cpu_resume) 37 38ENTRY(armada_38x_cpu_resume) 39 /* do we need it for Armada 38x*/ 40ARM_BE8(setend be ) @ go BE8 if entered LE 41 bl v7_invalidate_l1 42 bl armada_38x_scu_power_up 43 b cpu_resume 44ENDPROC(armada_38x_cpu_resume) 45 46.global mvebu_boot_wa_start 47.global mvebu_boot_wa_end 48 49/* The following code will be executed from SRAM */ 50ENTRY(mvebu_boot_wa_start) 51mvebu_boot_wa_start: 52ARM_BE8(setend be) 53 adr r0, 1f 54 ldr r0, [r0] @ load the address of the 55 @ resume register 56 ldr r0, [r0] @ load the value in the 57 @ resume register 58ARM_BE8(rev r0, r0) @ the value is stored LE 59 mov pc, r0 @ jump to this value 60/* 61 * the last word of this piece of code will be filled by the physical 62 * address of the boot address register just after being copied in SRAM 63 */ 641: 65 .long . 66mvebu_boot_wa_end: 67ENDPROC(mvebu_boot_wa_end) 68