1/* 2 * Copyright (C) 2014 Marvell 3 * 4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 5 * Gregory Clement <gregory.clement@free-electrons.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/linkage.h> 13#include <asm/assembler.h> 14 15/* 16 * This is the entry point through which CPUs exiting cpuidle deep 17 * idle state are going. 18 */ 19ENTRY(armada_370_xp_cpu_resume) 20ARM_BE8(setend be ) @ go BE8 if entered LE 21 bl ll_add_cpu_to_smp_group 22 bl ll_enable_coherency 23 b cpu_resume 24ENDPROC(armada_370_xp_cpu_resume) 25 26.global mvebu_boot_wa_start 27.global mvebu_boot_wa_end 28 29/* The following code will be executed from SRAM */ 30ENTRY(mvebu_boot_wa_start) 31mvebu_boot_wa_start: 32ARM_BE8(setend be) 33 adr r0, 1f 34 ldr r0, [r0] @ load the address of the 35 @ resume register 36 ldr r0, [r0] @ load the value in the 37 @ resume register 38ARM_BE8(rev r0, r0) @ the value is stored LE 39 mov pc, r0 @ jump to this value 40/* 41 * the last word of this piece of code will be filled by the physical 42 * address of the boot address register just after being copied in SRAM 43 */ 441: 45 .long . 46mvebu_boot_wa_end: 47ENDPROC(mvebu_boot_wa_end) 48