16509dc74SThomas Petazzoni/* 26509dc74SThomas Petazzoni * Copyright (C) 2014 Marvell 36509dc74SThomas Petazzoni * 46509dc74SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 56509dc74SThomas Petazzoni * Gregory Clement <gregory.clement@free-electrons.com> 66509dc74SThomas Petazzoni * 76509dc74SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 86509dc74SThomas Petazzoni * License version 2. This program is licensed "as is" without any 96509dc74SThomas Petazzoni * warranty of any kind, whether express or implied. 106509dc74SThomas Petazzoni */ 116509dc74SThomas Petazzoni 126509dc74SThomas Petazzoni#include <linux/linkage.h> 136509dc74SThomas Petazzoni#include <asm/assembler.h> 146509dc74SThomas Petazzoni 15f746ac32SGregory CLEMENT 16f746ac32SGregory CLEMENTENTRY(armada_38x_scu_power_up) 17f746ac32SGregory CLEMENT mrc p15, 4, r1, c15, c0 @ get SCU base address 18f746ac32SGregory CLEMENT orr r1, r1, #0x8 @ SCU CPU Power Status Register 19969ad77cSStefan Agner mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID 20f746ac32SGregory CLEMENT and r0, r0, #15 21f746ac32SGregory CLEMENT add r1, r1, r0 22f746ac32SGregory CLEMENT mov r0, #0x0 23f746ac32SGregory CLEMENT strb r0, [r1] @ switch SCU power state to Normal mode 24f746ac32SGregory CLEMENT ret lr 25f746ac32SGregory CLEMENTENDPROC(armada_38x_scu_power_up) 26f746ac32SGregory CLEMENT 276509dc74SThomas Petazzoni/* 286509dc74SThomas Petazzoni * This is the entry point through which CPUs exiting cpuidle deep 296509dc74SThomas Petazzoni * idle state are going. 306509dc74SThomas Petazzoni */ 316509dc74SThomas PetazzoniENTRY(armada_370_xp_cpu_resume) 326509dc74SThomas PetazzoniARM_BE8(setend be ) @ go BE8 if entered LE 3377ea46d1SThomas Petazzoni /* 3477ea46d1SThomas Petazzoni * Disable the MMU that might have been enabled in BootROM if 3577ea46d1SThomas Petazzoni * this code is used in the resume path of a suspend/resume 3677ea46d1SThomas Petazzoni * cycle. 3777ea46d1SThomas Petazzoni */ 3877ea46d1SThomas Petazzoni mrc p15, 0, r1, c1, c0, 0 3977ea46d1SThomas Petazzoni bic r1, #1 4077ea46d1SThomas Petazzoni mcr p15, 0, r1, c1, c0, 0 416509dc74SThomas Petazzoni bl ll_add_cpu_to_smp_group 426509dc74SThomas Petazzoni bl ll_enable_coherency 436509dc74SThomas Petazzoni b cpu_resume 446509dc74SThomas PetazzoniENDPROC(armada_370_xp_cpu_resume) 456509dc74SThomas Petazzoni 46e53b1fd4SGregory CLEMENTENTRY(armada_38x_cpu_resume) 47e53b1fd4SGregory CLEMENT /* do we need it for Armada 38x*/ 48e53b1fd4SGregory CLEMENTARM_BE8(setend be ) @ go BE8 if entered LE 49e53b1fd4SGregory CLEMENT bl v7_invalidate_l1 50f746ac32SGregory CLEMENT bl armada_38x_scu_power_up 51e53b1fd4SGregory CLEMENT b cpu_resume 52e53b1fd4SGregory CLEMENTENDPROC(armada_38x_cpu_resume) 53e53b1fd4SGregory CLEMENT 543076cc58SGregory CLEMENT.global mvebu_boot_wa_start 553076cc58SGregory CLEMENT.global mvebu_boot_wa_end 563076cc58SGregory CLEMENT 573076cc58SGregory CLEMENT/* The following code will be executed from SRAM */ 583076cc58SGregory CLEMENTENTRY(mvebu_boot_wa_start) 593076cc58SGregory CLEMENTARM_BE8(setend be) 603076cc58SGregory CLEMENT adr r0, 1f 613076cc58SGregory CLEMENT ldr r0, [r0] @ load the address of the 623076cc58SGregory CLEMENT @ resume register 633076cc58SGregory CLEMENT ldr r0, [r0] @ load the value in the 643076cc58SGregory CLEMENT @ resume register 653076cc58SGregory CLEMENTARM_BE8(rev r0, r0) @ the value is stored LE 663076cc58SGregory CLEMENT mov pc, r0 @ jump to this value 673076cc58SGregory CLEMENT/* 683076cc58SGregory CLEMENT * the last word of this piece of code will be filled by the physical 693076cc58SGregory CLEMENT * address of the boot address register just after being copied in SRAM 703076cc58SGregory CLEMENT */ 713076cc58SGregory CLEMENT1: 723076cc58SGregory CLEMENT .long . 733076cc58SGregory CLEMENTmvebu_boot_wa_end: 743076cc58SGregory CLEMENTENDPROC(mvebu_boot_wa_end) 75