16509dc74SThomas Petazzoni/* 26509dc74SThomas Petazzoni * Copyright (C) 2014 Marvell 36509dc74SThomas Petazzoni * 46509dc74SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 56509dc74SThomas Petazzoni * Gregory Clement <gregory.clement@free-electrons.com> 66509dc74SThomas Petazzoni * 76509dc74SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 86509dc74SThomas Petazzoni * License version 2. This program is licensed "as is" without any 96509dc74SThomas Petazzoni * warranty of any kind, whether express or implied. 106509dc74SThomas Petazzoni */ 116509dc74SThomas Petazzoni 126509dc74SThomas Petazzoni#include <linux/linkage.h> 136509dc74SThomas Petazzoni#include <asm/assembler.h> 146509dc74SThomas Petazzoni 156509dc74SThomas Petazzoni/* 166509dc74SThomas Petazzoni * This is the entry point through which CPUs exiting cpuidle deep 176509dc74SThomas Petazzoni * idle state are going. 186509dc74SThomas Petazzoni */ 196509dc74SThomas PetazzoniENTRY(armada_370_xp_cpu_resume) 206509dc74SThomas PetazzoniARM_BE8(setend be ) @ go BE8 if entered LE 2177ea46d1SThomas Petazzoni /* 2277ea46d1SThomas Petazzoni * Disable the MMU that might have been enabled in BootROM if 2377ea46d1SThomas Petazzoni * this code is used in the resume path of a suspend/resume 2477ea46d1SThomas Petazzoni * cycle. 2577ea46d1SThomas Petazzoni */ 2677ea46d1SThomas Petazzoni mrc p15, 0, r1, c1, c0, 0 2777ea46d1SThomas Petazzoni bic r1, #1 2877ea46d1SThomas Petazzoni mcr p15, 0, r1, c1, c0, 0 296509dc74SThomas Petazzoni bl ll_add_cpu_to_smp_group 306509dc74SThomas Petazzoni bl ll_enable_coherency 316509dc74SThomas Petazzoni b cpu_resume 326509dc74SThomas PetazzoniENDPROC(armada_370_xp_cpu_resume) 336509dc74SThomas Petazzoni 34e53b1fd4SGregory CLEMENTENTRY(armada_38x_cpu_resume) 35e53b1fd4SGregory CLEMENT /* do we need it for Armada 38x*/ 36e53b1fd4SGregory CLEMENTARM_BE8(setend be ) @ go BE8 if entered LE 37e53b1fd4SGregory CLEMENT bl v7_invalidate_l1 38e53b1fd4SGregory CLEMENT mrc p15, 4, r1, c15, c0 @ get SCU base address 39e53b1fd4SGregory CLEMENT orr r1, r1, #0x8 @ SCU CPU Power Status Register 40e53b1fd4SGregory CLEMENT mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID 41e53b1fd4SGregory CLEMENT and r0, r0, #15 42e53b1fd4SGregory CLEMENT add r1, r1, r0 43e53b1fd4SGregory CLEMENT mov r0, #0x0 44e53b1fd4SGregory CLEMENT strb r0, [r1] @ switch SCU power state to Normal mode 45e53b1fd4SGregory CLEMENT b cpu_resume 46e53b1fd4SGregory CLEMENTENDPROC(armada_38x_cpu_resume) 47e53b1fd4SGregory CLEMENT 483076cc58SGregory CLEMENT.global mvebu_boot_wa_start 493076cc58SGregory CLEMENT.global mvebu_boot_wa_end 503076cc58SGregory CLEMENT 513076cc58SGregory CLEMENT/* The following code will be executed from SRAM */ 523076cc58SGregory CLEMENTENTRY(mvebu_boot_wa_start) 533076cc58SGregory CLEMENTmvebu_boot_wa_start: 543076cc58SGregory CLEMENTARM_BE8(setend be) 553076cc58SGregory CLEMENT adr r0, 1f 563076cc58SGregory CLEMENT ldr r0, [r0] @ load the address of the 573076cc58SGregory CLEMENT @ resume register 583076cc58SGregory CLEMENT ldr r0, [r0] @ load the value in the 593076cc58SGregory CLEMENT @ resume register 603076cc58SGregory CLEMENTARM_BE8(rev r0, r0) @ the value is stored LE 613076cc58SGregory CLEMENT mov pc, r0 @ jump to this value 623076cc58SGregory CLEMENT/* 633076cc58SGregory CLEMENT * the last word of this piece of code will be filled by the physical 643076cc58SGregory CLEMENT * address of the boot address register just after being copied in SRAM 653076cc58SGregory CLEMENT */ 663076cc58SGregory CLEMENT1: 673076cc58SGregory CLEMENT .long . 683076cc58SGregory CLEMENTmvebu_boot_wa_end: 693076cc58SGregory CLEMENTENDPROC(mvebu_boot_wa_end) 70