xref: /openbmc/linux/arch/arm/mach-mvebu/pmsu.c (revision d2999e1b)
1 /*
2  * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
3  *
4  * Copyright (C) 2012 Marvell
5  *
6  * Yehuda Yitschak <yehuday@marvell.com>
7  * Gregory Clement <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9  *
10  * This file is licensed under the terms of the GNU General Public
11  * License version 2.  This program is licensed "as is" without any
12  * warranty of any kind, whether express or implied.
13  *
14  * The Armada 370 and Armada XP SOCs have a power management service
15  * unit which is responsible for powering down and waking up CPUs and
16  * other SOC units
17  */
18 
19 #define pr_fmt(fmt) "mvebu-pmsu: " fmt
20 
21 #include <linux/cpu_pm.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/of_address.h>
25 #include <linux/io.h>
26 #include <linux/platform_device.h>
27 #include <linux/smp.h>
28 #include <linux/resource.h>
29 #include <asm/cacheflush.h>
30 #include <asm/cp15.h>
31 #include <asm/smp_plat.h>
32 #include <asm/suspend.h>
33 #include <asm/tlbflush.h>
34 #include "common.h"
35 
36 static void __iomem *pmsu_mp_base;
37 
38 #define PMSU_BASE_OFFSET    0x100
39 #define PMSU_REG_SIZE	    0x1000
40 
41 /* PMSU MP registers */
42 #define PMSU_CONTROL_AND_CONFIG(cpu)	    ((cpu * 0x100) + 0x104)
43 #define PMSU_CONTROL_AND_CONFIG_DFS_REQ		BIT(18)
44 #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ	BIT(16)
45 #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN	BIT(20)
46 
47 #define PMSU_CPU_POWER_DOWN_CONTROL(cpu)    ((cpu * 0x100) + 0x108)
48 
49 #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP	BIT(0)
50 
51 #define PMSU_STATUS_AND_MASK(cpu)	    ((cpu * 0x100) + 0x10c)
52 #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT	BIT(16)
53 #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT	BIT(17)
54 #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP		BIT(20)
55 #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP		BIT(21)
56 #define PMSU_STATUS_AND_MASK_DBG_WAKEUP		BIT(22)
57 #define PMSU_STATUS_AND_MASK_IRQ_MASK		BIT(24)
58 #define PMSU_STATUS_AND_MASK_FIQ_MASK		BIT(25)
59 
60 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
61 
62 /* PMSU fabric registers */
63 #define L2C_NFABRIC_PM_CTL		    0x4
64 #define L2C_NFABRIC_PM_CTL_PWR_DOWN		BIT(20)
65 
66 extern void ll_disable_coherency(void);
67 extern void ll_enable_coherency(void);
68 
69 static struct platform_device armada_xp_cpuidle_device = {
70 	.name = "cpuidle-armada-370-xp",
71 };
72 
73 static struct of_device_id of_pmsu_table[] = {
74 	{ .compatible = "marvell,armada-370-pmsu", },
75 	{ .compatible = "marvell,armada-370-xp-pmsu", },
76 	{ .compatible = "marvell,armada-380-pmsu", },
77 	{ /* end of list */ },
78 };
79 
80 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
81 {
82 	writel(virt_to_phys(boot_addr), pmsu_mp_base +
83 		PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
84 }
85 
86 static int __init armada_370_xp_pmsu_init(void)
87 {
88 	struct device_node *np;
89 	struct resource res;
90 	int ret = 0;
91 
92 	np = of_find_matching_node(NULL, of_pmsu_table);
93 	if (!np)
94 		return 0;
95 
96 	pr_info("Initializing Power Management Service Unit\n");
97 
98 	if (of_address_to_resource(np, 0, &res)) {
99 		pr_err("unable to get resource\n");
100 		ret = -ENOENT;
101 		goto out;
102 	}
103 
104 	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
105 		pr_warn(FW_WARN "deprecated pmsu binding\n");
106 		res.start = res.start - PMSU_BASE_OFFSET;
107 		res.end = res.start + PMSU_REG_SIZE - 1;
108 	}
109 
110 	if (!request_mem_region(res.start, resource_size(&res),
111 				np->full_name)) {
112 		pr_err("unable to request region\n");
113 		ret = -EBUSY;
114 		goto out;
115 	}
116 
117 	pmsu_mp_base = ioremap(res.start, resource_size(&res));
118 	if (!pmsu_mp_base) {
119 		pr_err("unable to map registers\n");
120 		release_mem_region(res.start, resource_size(&res));
121 		ret = -ENOMEM;
122 		goto out;
123 	}
124 
125  out:
126 	of_node_put(np);
127 	return ret;
128 }
129 
130 static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
131 {
132 	u32 reg;
133 
134 	if (pmsu_mp_base == NULL)
135 		return;
136 
137 	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
138 	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
139 	reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
140 	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
141 }
142 
143 static void armada_370_xp_cpu_resume(void)
144 {
145 	asm volatile("bl    ll_add_cpu_to_smp_group\n\t"
146 		     "bl    ll_enable_coherency\n\t"
147 		     "b	    cpu_resume\n\t");
148 }
149 
150 /* No locking is needed because we only access per-CPU registers */
151 void armada_370_xp_pmsu_idle_prepare(bool deepidle)
152 {
153 	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
154 	u32 reg;
155 
156 	if (pmsu_mp_base == NULL)
157 		return;
158 
159 	/*
160 	 * Adjust the PMSU configuration to wait for WFI signal, enable
161 	 * IRQ and FIQ as wakeup events, set wait for snoop queue empty
162 	 * indication and mask IRQ and FIQ from CPU
163 	 */
164 	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
165 	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |
166 	       PMSU_STATUS_AND_MASK_IRQ_WAKEUP       |
167 	       PMSU_STATUS_AND_MASK_FIQ_WAKEUP       |
168 	       PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
169 	       PMSU_STATUS_AND_MASK_IRQ_MASK         |
170 	       PMSU_STATUS_AND_MASK_FIQ_MASK;
171 	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
172 
173 	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
174 	/* ask HW to power down the L2 Cache if needed */
175 	if (deepidle)
176 		reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
177 
178 	/* request power down */
179 	reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
180 	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
181 
182 	/* Disable snoop disable by HW - SW is taking care of it */
183 	reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
184 	reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
185 	writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
186 }
187 
188 static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
189 {
190 	armada_370_xp_pmsu_idle_prepare(deepidle);
191 
192 	v7_exit_coherency_flush(all);
193 
194 	ll_disable_coherency();
195 
196 	dsb();
197 
198 	wfi();
199 
200 	/* If we are here, wfi failed. As processors run out of
201 	 * coherency for some time, tlbs might be stale, so flush them
202 	 */
203 	local_flush_tlb_all();
204 
205 	ll_enable_coherency();
206 
207 	/* Test the CR_C bit and set it if it was cleared */
208 	asm volatile(
209 	"mrc	p15, 0, %0, c1, c0, 0 \n\t"
210 	"tst	%0, #(1 << 2) \n\t"
211 	"orreq	%0, %0, #(1 << 2) \n\t"
212 	"mcreq	p15, 0, %0, c1, c0, 0 \n\t"
213 	"isb	"
214 	: : "r" (0));
215 
216 	pr_warn("Failed to suspend the system\n");
217 
218 	return 0;
219 }
220 
221 static int armada_370_xp_cpu_suspend(unsigned long deepidle)
222 {
223 	return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
224 }
225 
226 /* No locking is needed because we only access per-CPU registers */
227 static noinline void armada_370_xp_pmsu_idle_restore(void)
228 {
229 	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
230 	u32 reg;
231 
232 	if (pmsu_mp_base == NULL)
233 		return;
234 
235 	/* cancel ask HW to power down the L2 Cache if possible */
236 	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
237 	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
238 	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
239 
240 	/* cancel Enable wakeup events and mask interrupts */
241 	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
242 	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
243 	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
244 	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
245 	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
246 	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
247 }
248 
249 static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
250 				    unsigned long action, void *hcpu)
251 {
252 	if (action == CPU_PM_ENTER) {
253 		unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
254 		mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
255 	} else if (action == CPU_PM_EXIT) {
256 		armada_370_xp_pmsu_idle_restore();
257 	}
258 
259 	return NOTIFY_OK;
260 }
261 
262 static struct notifier_block armada_370_xp_cpu_pm_notifier = {
263 	.notifier_call = armada_370_xp_cpu_pm_notify,
264 };
265 
266 int __init armada_370_xp_cpu_pm_init(void)
267 {
268 	struct device_node *np;
269 
270 	/*
271 	 * Check that all the requirements are available to enable
272 	 * cpuidle. So far, it is only supported on Armada XP, cpuidle
273 	 * needs the coherency fabric and the PMSU enabled
274 	 */
275 
276 	if (!of_machine_is_compatible("marvell,armadaxp"))
277 		return 0;
278 
279 	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
280 	if (!np)
281 		return 0;
282 	of_node_put(np);
283 
284 	np = of_find_matching_node(NULL, of_pmsu_table);
285 	if (!np)
286 		return 0;
287 	of_node_put(np);
288 
289 	armada_370_xp_pmsu_enable_l2_powerdown_onidle();
290 	armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
291 	platform_device_register(&armada_xp_cpuidle_device);
292 	cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
293 
294 	return 0;
295 }
296 
297 arch_initcall(armada_370_xp_cpu_pm_init);
298 early_initcall(armada_370_xp_pmsu_init);
299