1 /* 2 * Suspend/resume support. Currently supporting Armada XP only. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/cpu_pm.h> 14 #include <linux/delay.h> 15 #include <linux/gpio.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/mbus.h> 19 #include <linux/of_address.h> 20 #include <linux/suspend.h> 21 #include <asm/cacheflush.h> 22 #include <asm/outercache.h> 23 #include <asm/suspend.h> 24 25 #include "coherency.h" 26 #include "pmsu.h" 27 28 #define SDRAM_CONFIG_OFFS 0x0 29 #define SDRAM_CONFIG_SR_MODE_BIT BIT(24) 30 #define SDRAM_OPERATION_OFFS 0x18 31 #define SDRAM_OPERATION_SELF_REFRESH 0x7 32 #define SDRAM_DLB_EVICTION_OFFS 0x30c 33 #define SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff 34 35 static void (*mvebu_board_pm_enter)(void __iomem *sdram_reg, u32 srcmd); 36 static void __iomem *sdram_ctrl; 37 38 static int mvebu_pm_powerdown(unsigned long data) 39 { 40 u32 reg, srcmd; 41 42 flush_cache_all(); 43 outer_flush_all(); 44 45 /* 46 * Issue a Data Synchronization Barrier instruction to ensure 47 * that all state saving has been completed. 48 */ 49 dsb(); 50 51 /* Flush the DLB and wait ~7 usec */ 52 reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); 53 reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK; 54 writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); 55 56 udelay(7); 57 58 /* Set DRAM in battery backup mode */ 59 reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS); 60 reg &= ~SDRAM_CONFIG_SR_MODE_BIT; 61 writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); 62 63 /* Prepare to go to self-refresh */ 64 65 srcmd = readl(sdram_ctrl + SDRAM_OPERATION_OFFS); 66 srcmd &= ~0x1F; 67 srcmd |= SDRAM_OPERATION_SELF_REFRESH; 68 69 mvebu_board_pm_enter(sdram_ctrl + SDRAM_OPERATION_OFFS, srcmd); 70 71 return 0; 72 } 73 74 #define BOOT_INFO_ADDR 0x3000 75 #define BOOT_MAGIC_WORD 0xdeadb002 76 #define BOOT_MAGIC_LIST_END 0xffffffff 77 78 /* 79 * Those registers are accessed before switching the internal register 80 * base, which is why we hardcode the 0xd0000000 base address, the one 81 * used by the SoC out of reset. 82 */ 83 #define MBUS_WINDOW_12_CTRL 0xd00200b0 84 #define MBUS_INTERNAL_REG_ADDRESS 0xd0020080 85 86 #define SDRAM_WIN_BASE_REG(x) (0x20180 + (0x8*x)) 87 #define SDRAM_WIN_CTRL_REG(x) (0x20184 + (0x8*x)) 88 89 static phys_addr_t mvebu_internal_reg_base(void) 90 { 91 struct device_node *np; 92 __be32 in_addr[2]; 93 94 np = of_find_node_by_name(NULL, "internal-regs"); 95 BUG_ON(!np); 96 97 /* 98 * Ask the DT what is the internal register address on this 99 * platform. In the mvebu-mbus DT binding, 0xf0010000 100 * corresponds to the internal register window. 101 */ 102 in_addr[0] = cpu_to_be32(0xf0010000); 103 in_addr[1] = 0x0; 104 105 return of_translate_address(np, in_addr); 106 } 107 108 static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr) 109 { 110 phys_addr_t resume_pc; 111 112 resume_pc = virt_to_phys(armada_370_xp_cpu_resume); 113 114 /* 115 * The bootloader expects the first two words to be a magic 116 * value (BOOT_MAGIC_WORD), followed by the address of the 117 * resume code to jump to. Then, it expects a sequence of 118 * (address, value) pairs, which can be used to restore the 119 * value of certain registers. This sequence must end with the 120 * BOOT_MAGIC_LIST_END magic value. 121 */ 122 123 writel(BOOT_MAGIC_WORD, store_addr++); 124 writel(resume_pc, store_addr++); 125 126 /* 127 * Some platforms remap their internal register base address 128 * to 0xf1000000. However, out of reset, window 12 starts at 129 * 0xf0000000 and ends at 0xf7ffffff, which would overlap with 130 * the internal registers. Therefore, disable window 12. 131 */ 132 writel(MBUS_WINDOW_12_CTRL, store_addr++); 133 writel(0x0, store_addr++); 134 135 /* 136 * Set the internal register base address to the value 137 * expected by Linux, as read from the Device Tree. 138 */ 139 writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++); 140 writel(mvebu_internal_reg_base(), store_addr++); 141 142 /* 143 * Ask the mvebu-mbus driver to store the SDRAM window 144 * configuration, which has to be restored by the bootloader 145 * before re-entering the kernel on resume. 146 */ 147 store_addr += mvebu_mbus_save_cpu_target(store_addr); 148 149 writel(BOOT_MAGIC_LIST_END, store_addr); 150 } 151 152 static int mvebu_pm_store_bootinfo(void) 153 { 154 u32 *store_addr; 155 156 store_addr = phys_to_virt(BOOT_INFO_ADDR); 157 158 if (of_machine_is_compatible("marvell,armadaxp")) 159 mvebu_pm_store_armadaxp_bootinfo(store_addr); 160 else 161 return -ENODEV; 162 163 return 0; 164 } 165 166 static int mvebu_enter_suspend(void) 167 { 168 int ret; 169 170 ret = mvebu_pm_store_bootinfo(); 171 if (ret) 172 return ret; 173 174 cpu_pm_enter(); 175 176 cpu_suspend(0, mvebu_pm_powerdown); 177 178 outer_resume(); 179 180 mvebu_v7_pmsu_idle_exit(); 181 182 set_cpu_coherent(); 183 184 cpu_pm_exit(); 185 return 0; 186 } 187 188 static int mvebu_pm_enter(suspend_state_t state) 189 { 190 switch (state) { 191 case PM_SUSPEND_STANDBY: 192 cpu_do_idle(); 193 break; 194 case PM_SUSPEND_MEM: 195 pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n"); 196 return mvebu_enter_suspend(); 197 default: 198 return -EINVAL; 199 } 200 return 0; 201 } 202 203 static int mvebu_pm_valid(suspend_state_t state) 204 { 205 if (state == PM_SUSPEND_STANDBY) 206 return 1; 207 208 if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL) 209 return 1; 210 211 return 0; 212 } 213 214 static const struct platform_suspend_ops mvebu_pm_ops = { 215 .enter = mvebu_pm_enter, 216 .valid = mvebu_pm_valid, 217 }; 218 219 static int __init mvebu_pm_init(void) 220 { 221 if (!of_machine_is_compatible("marvell,armadaxp") && 222 !of_machine_is_compatible("marvell,armada370") && 223 !of_machine_is_compatible("marvell,armada380") && 224 !of_machine_is_compatible("marvell,armada390")) 225 return -ENODEV; 226 227 suspend_set_ops(&mvebu_pm_ops); 228 229 return 0; 230 } 231 232 233 late_initcall(mvebu_pm_init); 234 235 int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg, 236 u32 srcmd)) 237 { 238 struct device_node *np; 239 struct resource res; 240 241 np = of_find_compatible_node(NULL, NULL, 242 "marvell,armada-xp-sdram-controller"); 243 if (!np) 244 return -ENODEV; 245 246 if (of_address_to_resource(np, 0, &res)) { 247 of_node_put(np); 248 return -ENODEV; 249 } 250 251 if (!request_mem_region(res.start, resource_size(&res), 252 np->full_name)) { 253 of_node_put(np); 254 return -EBUSY; 255 } 256 257 sdram_ctrl = ioremap(res.start, resource_size(&res)); 258 if (!sdram_ctrl) { 259 release_mem_region(res.start, resource_size(&res)); 260 of_node_put(np); 261 return -ENOMEM; 262 } 263 264 of_node_put(np); 265 266 mvebu_board_pm_enter = board_pm_enter; 267 268 return 0; 269 } 270