1 /* 2 * ID and revision information for mvebu SoCs 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 * 12 * All the mvebu SoCs have information related to their variant and 13 * revision that can be read from the PCI control register. This is 14 * done before the PCI initialization to avoid any conflict. Once the 15 * ID and revision are retrieved, the mapping is freed. 16 */ 17 18 #define pr_fmt(fmt) "mvebu-soc-id: " fmt 19 20 #include <linux/clk.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/slab.h> 27 #include <linux/sys_soc.h> 28 #include "mvebu-soc-id.h" 29 30 #define PCIE_DEV_ID_OFF 0x0 31 #define PCIE_DEV_REV_OFF 0x8 32 33 #define SOC_ID_MASK 0xFFFF0000 34 #define SOC_REV_MASK 0xFF 35 36 static u32 soc_dev_id; 37 static u32 soc_rev; 38 static bool is_id_valid; 39 40 static const struct of_device_id mvebu_pcie_of_match_table[] = { 41 { .compatible = "marvell,armada-xp-pcie", }, 42 { .compatible = "marvell,armada-370-pcie", }, 43 { .compatible = "marvell,kirkwood-pcie" }, 44 {}, 45 }; 46 47 int mvebu_get_soc_id(u32 *dev, u32 *rev) 48 { 49 if (is_id_valid) { 50 *dev = soc_dev_id; 51 *rev = soc_rev; 52 return 0; 53 } else 54 return -1; 55 } 56 57 static int __init mvebu_soc_id_init(void) 58 { 59 struct device_node *np; 60 int ret = 0; 61 void __iomem *pci_base; 62 struct clk *clk; 63 struct device_node *child; 64 65 np = of_find_matching_node(NULL, mvebu_pcie_of_match_table); 66 if (!np) 67 return ret; 68 69 /* 70 * ID and revision are available from any port, so we 71 * just pick the first one 72 */ 73 child = of_get_next_child(np, NULL); 74 if (child == NULL) { 75 pr_err("cannot get pci node\n"); 76 ret = -ENOMEM; 77 goto clk_err; 78 } 79 80 clk = of_clk_get_by_name(child, NULL); 81 if (IS_ERR(clk)) { 82 pr_err("cannot get clock\n"); 83 ret = -ENOMEM; 84 goto clk_err; 85 } 86 87 ret = clk_prepare_enable(clk); 88 if (ret) { 89 pr_err("cannot enable clock\n"); 90 goto clk_err; 91 } 92 93 pci_base = of_iomap(child, 0); 94 if (pci_base == NULL) { 95 pr_err("cannot map registers\n"); 96 ret = -ENOMEM; 97 goto res_ioremap; 98 } 99 100 /* SoC ID */ 101 soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16; 102 103 /* SoC revision */ 104 soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK; 105 106 is_id_valid = true; 107 108 pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev); 109 110 iounmap(pci_base); 111 112 res_ioremap: 113 /* 114 * If the PCIe unit is actually enabled and we have PCI 115 * support in the kernel, we intentionally do not release the 116 * reference to the clock. We want to keep it running since 117 * the bootloader does some PCIe link configuration that the 118 * kernel is for now unable to do, and gating the clock would 119 * make us loose this precious configuration. 120 */ 121 if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) { 122 clk_disable_unprepare(clk); 123 clk_put(clk); 124 } 125 126 clk_err: 127 of_node_put(child); 128 of_node_put(np); 129 130 return ret; 131 } 132 early_initcall(mvebu_soc_id_init); 133 134 static int __init mvebu_soc_device(void) 135 { 136 struct soc_device_attribute *soc_dev_attr; 137 struct soc_device *soc_dev; 138 139 /* Also protects against running on non-mvebu systems */ 140 if (!is_id_valid) 141 return 0; 142 143 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 144 if (!soc_dev_attr) 145 return -ENOMEM; 146 147 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Marvell"); 148 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", soc_rev); 149 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%X", soc_dev_id); 150 151 soc_dev = soc_device_register(soc_dev_attr); 152 if (IS_ERR(soc_dev)) { 153 kfree(soc_dev_attr->family); 154 kfree(soc_dev_attr->revision); 155 kfree(soc_dev_attr->soc_id); 156 kfree(soc_dev_attr); 157 } 158 159 return 0; 160 } 161 postcore_initcall(mvebu_soc_device); 162