1 /*
2  * ID and revision information for mvebu SoCs
3  *
4  * Copyright (C) 2014 Marvell
5  *
6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  *
12  * All the mvebu SoCs have information related to their variant and
13  * revision that can be read from the PCI control register. This is
14  * done before the PCI initialization to avoid any conflict. Once the
15  * ID and revision are retrieved, the mapping is freed.
16  */
17 
18 #define pr_fmt(fmt) "mvebu-soc-id: " fmt
19 
20 #include <linux/clk.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include "mvebu-soc-id.h"
27 
28 #define PCIE_DEV_ID_OFF		0x0
29 #define PCIE_DEV_REV_OFF	0x8
30 
31 #define SOC_ID_MASK	    0xFFFF0000
32 #define SOC_REV_MASK	    0xFF
33 
34 static u32 soc_dev_id;
35 static u32 soc_rev;
36 static bool is_id_valid;
37 
38 static const struct of_device_id mvebu_pcie_of_match_table[] = {
39 	{ .compatible = "marvell,armada-xp-pcie", },
40 	{ .compatible = "marvell,armada-370-pcie", },
41 	{},
42 };
43 
44 int mvebu_get_soc_id(u32 *dev, u32 *rev)
45 {
46 	if (is_id_valid) {
47 		*dev = soc_dev_id;
48 		*rev = soc_rev;
49 		return 0;
50 	} else
51 		return -1;
52 }
53 
54 static int __init mvebu_soc_id_init(void)
55 {
56 	struct device_node *np;
57 	int ret = 0;
58 	void __iomem *pci_base;
59 	struct clk *clk;
60 	struct device_node *child;
61 
62 	np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
63 	if (!np)
64 		return ret;
65 
66 	/*
67 	 * ID and revision are available from any port, so we
68 	 * just pick the first one
69 	 */
70 	child = of_get_next_child(np, NULL);
71 	if (child == NULL) {
72 		pr_err("cannot get pci node\n");
73 		ret = -ENOMEM;
74 		goto clk_err;
75 	}
76 
77 	clk = of_clk_get_by_name(child, NULL);
78 	if (IS_ERR(clk)) {
79 		pr_err("cannot get clock\n");
80 		ret = -ENOMEM;
81 		goto clk_err;
82 	}
83 
84 	ret = clk_prepare_enable(clk);
85 	if (ret) {
86 		pr_err("cannot enable clock\n");
87 		goto clk_err;
88 	}
89 
90 	pci_base = of_iomap(child, 0);
91 	if (pci_base == NULL) {
92 		pr_err("cannot map registers\n");
93 		ret = -ENOMEM;
94 		goto res_ioremap;
95 	}
96 
97 	/* SoC ID */
98 	soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
99 
100 	/* SoC revision */
101 	soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
102 
103 	is_id_valid = true;
104 
105 	pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
106 
107 	iounmap(pci_base);
108 
109 res_ioremap:
110 	clk_disable_unprepare(clk);
111 
112 clk_err:
113 	of_node_put(child);
114 	of_node_put(np);
115 
116 	return ret;
117 }
118 core_initcall(mvebu_soc_id_init);
119 
120