145f5984aSGregory CLEMENT/* 245f5984aSGregory CLEMENT * SMP support: Entry point for secondary CPUs 345f5984aSGregory CLEMENT * 445f5984aSGregory CLEMENT * Copyright (C) 2012 Marvell 545f5984aSGregory CLEMENT * 645f5984aSGregory CLEMENT * Yehuda Yitschak <yehuday@marvell.com> 745f5984aSGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 845f5984aSGregory CLEMENT * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 945f5984aSGregory CLEMENT * 1045f5984aSGregory CLEMENT * This file is licensed under the terms of the GNU General Public 1145f5984aSGregory CLEMENT * License version 2. This program is licensed "as is" without any 1245f5984aSGregory CLEMENT * warranty of any kind, whether express or implied. 1345f5984aSGregory CLEMENT * 1445f5984aSGregory CLEMENT * This file implements the assembly entry point for secondary CPUs in 1545f5984aSGregory CLEMENT * an SMP kernel. The only thing we need to do is to add the CPU to 1645f5984aSGregory CLEMENT * the coherency fabric by writing to 2 registers. Currently the base 1745f5984aSGregory CLEMENT * register addresses are hard coded due to the early initialisation 1845f5984aSGregory CLEMENT * problems. 1945f5984aSGregory CLEMENT */ 2045f5984aSGregory CLEMENT 2145f5984aSGregory CLEMENT#include <linux/linkage.h> 2245f5984aSGregory CLEMENT#include <linux/init.h> 2345f5984aSGregory CLEMENT 2445f5984aSGregory CLEMENT/* 2545f5984aSGregory CLEMENT * At this stage the secondary CPUs don't have acces yet to the MMU, so 2645f5984aSGregory CLEMENT * we have to provide physical addresses 2745f5984aSGregory CLEMENT */ 2845f5984aSGregory CLEMENT#define ARMADA_XP_CFB_BASE 0xD0020200 2945f5984aSGregory CLEMENT 3045f5984aSGregory CLEMENT __CPUINIT 3145f5984aSGregory CLEMENT 3245f5984aSGregory CLEMENT/* 3345f5984aSGregory CLEMENT * Armada XP specific entry point for secondary CPUs. 3445f5984aSGregory CLEMENT * We add the CPU to the coherency fabric and then jump to secondary 3545f5984aSGregory CLEMENT * startup 3645f5984aSGregory CLEMENT */ 3745f5984aSGregory CLEMENTENTRY(armada_xp_secondary_startup) 3845f5984aSGregory CLEMENT 3945f5984aSGregory CLEMENT /* Read CPU id */ 4045f5984aSGregory CLEMENT mrc p15, 0, r1, c0, c0, 5 4145f5984aSGregory CLEMENT and r1, r1, #0xF 4245f5984aSGregory CLEMENT 4345f5984aSGregory CLEMENT /* Add CPU to coherency fabric */ 4445f5984aSGregory CLEMENT ldr r0, =ARMADA_XP_CFB_BASE 4545f5984aSGregory CLEMENT 4645f5984aSGregory CLEMENT bl ll_set_cpu_coherent 4745f5984aSGregory CLEMENT b secondary_startup 4845f5984aSGregory CLEMENT 4945f5984aSGregory CLEMENTENDPROC(armada_xp_secondary_startup) 50