1/* 2 * SMP support: Entry point for secondary CPUs of Marvell EBU 3 * Cortex-A9 based SOCs (Armada 375 and Armada 38x). 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15#include <linux/linkage.h> 16#include <linux/init.h> 17 18 __CPUINIT 19#define CPU_RESUME_ADDR_REG 0xf10182d4 20 21.global armada_375_smp_cpu1_enable_code_start 22.global armada_375_smp_cpu1_enable_code_end 23 24armada_375_smp_cpu1_enable_code_start: 25 ldr r0, [pc, #4] 26 ldr r1, [r0] 27 mov pc, r1 28 .word CPU_RESUME_ADDR_REG 29armada_375_smp_cpu1_enable_code_end: 30 31ENTRY(mvebu_cortex_a9_secondary_startup) 32 bl v7_invalidate_l1 33 b secondary_startup 34ENDPROC(mvebu_cortex_a9_secondary_startup) 35