1/* 2 * SMP support: Entry point for secondary CPUs of Marvell EBU 3 * Cortex-A9 based SOCs (Armada 375 and Armada 38x). 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15#include <linux/linkage.h> 16#include <linux/init.h> 17 18#include <asm/assembler.h> 19 20 __CPUINIT 21#define CPU_RESUME_ADDR_REG 0xf10182d4 22 23.global armada_375_smp_cpu1_enable_code_start 24.global armada_375_smp_cpu1_enable_code_end 25 26armada_375_smp_cpu1_enable_code_start: 27ARM_BE8(setend be) 28 adr r0, 1f 29 ldr r0, [r0] 30 ldr r1, [r0] 31ARM_BE8(rev r1, r1) 32 mov pc, r1 331: 34 .word CPU_RESUME_ADDR_REG 35armada_375_smp_cpu1_enable_code_end: 36 37ENTRY(mvebu_cortex_a9_secondary_startup) 38ARM_BE8(setend be) 39 bl v7_invalidate_l1 40 b secondary_startup 41ENDPROC(mvebu_cortex_a9_secondary_startup) 42