11ee89e22SGregory CLEMENT/* 21ee89e22SGregory CLEMENT * SMP support: Entry point for secondary CPUs of Marvell EBU 31ee89e22SGregory CLEMENT * Cortex-A9 based SOCs (Armada 375 and Armada 38x). 41ee89e22SGregory CLEMENT * 51ee89e22SGregory CLEMENT * Copyright (C) 2014 Marvell 61ee89e22SGregory CLEMENT * 71ee89e22SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 81ee89e22SGregory CLEMENT * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 91ee89e22SGregory CLEMENT * 101ee89e22SGregory CLEMENT * This file is licensed under the terms of the GNU General Public 111ee89e22SGregory CLEMENT * License version 2. This program is licensed "as is" without any 121ee89e22SGregory CLEMENT * warranty of any kind, whether express or implied. 131ee89e22SGregory CLEMENT */ 141ee89e22SGregory CLEMENT 151ee89e22SGregory CLEMENT#include <linux/linkage.h> 161ee89e22SGregory CLEMENT#include <linux/init.h> 171ee89e22SGregory CLEMENT 181ee89e22SGregory CLEMENT __CPUINIT 1987384cc0SGregory CLEMENT#define CPU_RESUME_ADDR_REG 0xf10182d4 2087384cc0SGregory CLEMENT 2187384cc0SGregory CLEMENT.global armada_375_smp_cpu1_enable_code_start 2287384cc0SGregory CLEMENT.global armada_375_smp_cpu1_enable_code_end 2387384cc0SGregory CLEMENT 2487384cc0SGregory CLEMENTarmada_375_smp_cpu1_enable_code_start: 2587384cc0SGregory CLEMENT ldr r0, [pc, #4] 2687384cc0SGregory CLEMENT ldr r1, [r0] 2787384cc0SGregory CLEMENT mov pc, r1 2887384cc0SGregory CLEMENT .word CPU_RESUME_ADDR_REG 2987384cc0SGregory CLEMENTarmada_375_smp_cpu1_enable_code_end: 3087384cc0SGregory CLEMENT 311ee89e22SGregory CLEMENTENTRY(mvebu_cortex_a9_secondary_startup) 321ee89e22SGregory CLEMENT bl v7_invalidate_l1 331ee89e22SGregory CLEMENT b secondary_startup 341ee89e22SGregory CLEMENTENDPROC(mvebu_cortex_a9_secondary_startup) 35