1 /* 2 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP 3 * platforms. 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Yehuda Yitschak <yehuday@marvell.com> 8 * Gregory Clement <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 * 15 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is 16 * responsible for ensuring hardware coherency between all CPUs and between 17 * CPUs and I/O masters. This file initializes the coherency fabric and 18 * supplies basic routines for configuring and controlling hardware coherency 19 */ 20 21 #define pr_fmt(fmt) "mvebu-coherency: " fmt 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/of_address.h> 26 #include <linux/io.h> 27 #include <linux/smp.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 #include <linux/mbus.h> 32 #include <linux/pci.h> 33 #include <asm/smp_plat.h> 34 #include <asm/cacheflush.h> 35 #include <asm/mach/map.h> 36 #include <asm/dma-mapping.h> 37 #include "coherency.h" 38 #include "mvebu-soc-id.h" 39 40 unsigned long coherency_phys_base; 41 void __iomem *coherency_base; 42 static void __iomem *coherency_cpu_base; 43 44 /* Coherency fabric registers */ 45 #define IO_SYNC_BARRIER_CTL_OFFSET 0x0 46 47 enum { 48 COHERENCY_FABRIC_TYPE_NONE, 49 COHERENCY_FABRIC_TYPE_ARMADA_370_XP, 50 COHERENCY_FABRIC_TYPE_ARMADA_375, 51 COHERENCY_FABRIC_TYPE_ARMADA_380, 52 }; 53 54 static const struct of_device_id of_coherency_table[] = { 55 {.compatible = "marvell,coherency-fabric", 56 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP }, 57 {.compatible = "marvell,armada-375-coherency-fabric", 58 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 }, 59 {.compatible = "marvell,armada-380-coherency-fabric", 60 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 }, 61 { /* end of list */ }, 62 }; 63 64 /* Functions defined in coherency_ll.S */ 65 int ll_enable_coherency(void); 66 void ll_add_cpu_to_smp_group(void); 67 68 int set_cpu_coherent(void) 69 { 70 if (!coherency_base) { 71 pr_warn("Can't make current CPU cache coherent.\n"); 72 pr_warn("Coherency fabric is not initialized\n"); 73 return 1; 74 } 75 76 ll_add_cpu_to_smp_group(); 77 return ll_enable_coherency(); 78 } 79 80 static int mvebu_hwcc_notifier(struct notifier_block *nb, 81 unsigned long event, void *__dev) 82 { 83 struct device *dev = __dev; 84 85 if (event != BUS_NOTIFY_ADD_DEVICE) 86 return NOTIFY_DONE; 87 set_dma_ops(dev, &arm_coherent_dma_ops); 88 89 return NOTIFY_OK; 90 } 91 92 static struct notifier_block mvebu_hwcc_nb = { 93 .notifier_call = mvebu_hwcc_notifier, 94 }; 95 96 static struct notifier_block mvebu_hwcc_pci_nb = { 97 .notifier_call = mvebu_hwcc_notifier, 98 }; 99 100 static void __init armada_370_coherency_init(struct device_node *np) 101 { 102 struct resource res; 103 104 of_address_to_resource(np, 0, &res); 105 coherency_phys_base = res.start; 106 /* 107 * Ensure secondary CPUs will see the updated value, 108 * which they read before they join the coherency 109 * fabric, and therefore before they are coherent with 110 * the boot CPU cache. 111 */ 112 sync_cache_w(&coherency_phys_base); 113 coherency_base = of_iomap(np, 0); 114 coherency_cpu_base = of_iomap(np, 1); 115 set_cpu_coherent(); 116 } 117 118 /* 119 * This ioremap hook is used on Armada 375/38x to ensure that PCIe 120 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This 121 * is needed as a workaround for a deadlock issue between the PCIe 122 * interface and the cache controller. 123 */ 124 static void __iomem * 125 armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size, 126 unsigned int mtype, void *caller) 127 { 128 struct resource pcie_mem; 129 130 mvebu_mbus_get_pcie_mem_aperture(&pcie_mem); 131 132 if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end) 133 mtype = MT_UNCACHED; 134 135 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 136 } 137 138 static void __init armada_375_380_coherency_init(struct device_node *np) 139 { 140 struct device_node *cache_dn; 141 142 coherency_cpu_base = of_iomap(np, 0); 143 arch_ioremap_caller = armada_pcie_wa_ioremap_caller; 144 145 /* 146 * We should switch the PL310 to I/O coherency mode only if 147 * I/O coherency is actually enabled. 148 */ 149 if (!coherency_available()) 150 return; 151 152 /* 153 * Add the PL310 property "arm,io-coherent". This makes sure the 154 * outer sync operation is not used, which allows to 155 * workaround the system erratum that causes deadlocks when 156 * doing PCIe in an SMP situation on Armada 375 and Armada 157 * 38x. 158 */ 159 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") { 160 struct property *p; 161 162 p = kzalloc(sizeof(*p), GFP_KERNEL); 163 p->name = kstrdup("arm,io-coherent", GFP_KERNEL); 164 of_add_property(cache_dn, p); 165 } 166 } 167 168 static int coherency_type(void) 169 { 170 struct device_node *np; 171 const struct of_device_id *match; 172 int type; 173 174 /* 175 * The coherency fabric is needed: 176 * - For coherency between processors on Armada XP, so only 177 * when SMP is enabled. 178 * - For coherency between the processor and I/O devices, but 179 * this coherency requires many pre-requisites (write 180 * allocate cache policy, shareable pages, SMP bit set) that 181 * are only meant in SMP situations. 182 * 183 * Note that this means that on Armada 370, there is currently 184 * no way to use hardware I/O coherency, because even when 185 * CONFIG_SMP is enabled, is_smp() returns false due to the 186 * Armada 370 being a single-core processor. To lift this 187 * limitation, we would have to find a way to make the cache 188 * policy set to write-allocate (on all Armada SoCs), and to 189 * set the shareable attribute in page tables (on all Armada 190 * SoCs except the Armada 370). Unfortunately, such decisions 191 * are taken very early in the kernel boot process, at a point 192 * where we don't know yet on which SoC we are running. 193 194 */ 195 if (!is_smp()) 196 return COHERENCY_FABRIC_TYPE_NONE; 197 198 np = of_find_matching_node_and_match(NULL, of_coherency_table, &match); 199 if (!np) 200 return COHERENCY_FABRIC_TYPE_NONE; 201 202 type = (int) match->data; 203 204 of_node_put(np); 205 206 return type; 207 } 208 209 int coherency_available(void) 210 { 211 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; 212 } 213 214 int __init coherency_init(void) 215 { 216 int type = coherency_type(); 217 struct device_node *np; 218 219 np = of_find_matching_node(NULL, of_coherency_table); 220 221 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) 222 armada_370_coherency_init(np); 223 else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 || 224 type == COHERENCY_FABRIC_TYPE_ARMADA_380) 225 armada_375_380_coherency_init(np); 226 227 of_node_put(np); 228 229 return 0; 230 } 231 232 static int __init coherency_late_init(void) 233 { 234 if (coherency_available()) 235 bus_register_notifier(&platform_bus_type, 236 &mvebu_hwcc_nb); 237 return 0; 238 } 239 240 postcore_initcall(coherency_late_init); 241 242 #if IS_ENABLED(CONFIG_PCI) 243 static int __init coherency_pci_init(void) 244 { 245 if (coherency_available()) 246 bus_register_notifier(&pci_bus_type, 247 &mvebu_hwcc_pci_nb); 248 return 0; 249 } 250 251 arch_initcall(coherency_pci_init); 252 #endif 253