1*0fdebc5eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24c811b99SArnd Bergmann /* 34c811b99SArnd Bergmann * Generic definitions for Marvell MV78xx0 SoC flavors: 44c811b99SArnd Bergmann * MV781x0 and MV782x0. 54c811b99SArnd Bergmann */ 64c811b99SArnd Bergmann 74c811b99SArnd Bergmann #ifndef __ASM_ARCH_MV78XX0_H 84c811b99SArnd Bergmann #define __ASM_ARCH_MV78XX0_H 94c811b99SArnd Bergmann 104c811b99SArnd Bergmann #include "irqs.h" 114c811b99SArnd Bergmann 124c811b99SArnd Bergmann /* 134c811b99SArnd Bergmann * Marvell MV78xx0 address maps. 144c811b99SArnd Bergmann * 154c811b99SArnd Bergmann * phys 164c811b99SArnd Bergmann * c0000000 PCIe Memory space 174c811b99SArnd Bergmann * f0800000 PCIe #0 I/O space 184c811b99SArnd Bergmann * f0900000 PCIe #1 I/O space 194c811b99SArnd Bergmann * f0a00000 PCIe #2 I/O space 204c811b99SArnd Bergmann * f0b00000 PCIe #3 I/O space 214c811b99SArnd Bergmann * f0c00000 PCIe #4 I/O space 224c811b99SArnd Bergmann * f0d00000 PCIe #5 I/O space 234c811b99SArnd Bergmann * f0e00000 PCIe #6 I/O space 244c811b99SArnd Bergmann * f0f00000 PCIe #7 I/O space 254c811b99SArnd Bergmann * f1000000 on-chip peripheral registers 264c811b99SArnd Bergmann * 274c811b99SArnd Bergmann * virt phys size 284c811b99SArnd Bergmann * fe400000 f102x000 16K core-specific peripheral registers 294c811b99SArnd Bergmann * fee00000 f0800000 64K PCIe #0 I/O space 304c811b99SArnd Bergmann * fee10000 f0900000 64K PCIe #1 I/O space 314c811b99SArnd Bergmann * fee20000 f0a00000 64K PCIe #2 I/O space 324c811b99SArnd Bergmann * fee30000 f0b00000 64K PCIe #3 I/O space 334c811b99SArnd Bergmann * fee40000 f0c00000 64K PCIe #4 I/O space 344c811b99SArnd Bergmann * fee50000 f0d00000 64K PCIe #5 I/O space 354c811b99SArnd Bergmann * fee60000 f0e00000 64K PCIe #6 I/O space 364c811b99SArnd Bergmann * fee70000 f0f00000 64K PCIe #7 I/O space 373584be9eSArnd Bergmann * fec00000 f1000000 1M on-chip peripheral registers 384c811b99SArnd Bergmann */ 394c811b99SArnd Bergmann #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 404c811b99SArnd Bergmann #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 414c811b99SArnd Bergmann #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) 424c811b99SArnd Bergmann #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 434c811b99SArnd Bergmann #define MV78XX0_CORE_REGS_SIZE SZ_16K 444c811b99SArnd Bergmann 454c811b99SArnd Bergmann #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 464c811b99SArnd Bergmann #define MV78XX0_PCIE_IO_SIZE SZ_1M 474c811b99SArnd Bergmann 484c811b99SArnd Bergmann #define MV78XX0_REGS_PHYS_BASE 0xf1000000 493584be9eSArnd Bergmann #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) 504c811b99SArnd Bergmann #define MV78XX0_REGS_SIZE SZ_1M 514c811b99SArnd Bergmann 524c811b99SArnd Bergmann #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 534c811b99SArnd Bergmann #define MV78XX0_PCIE_MEM_SIZE 0x30000000 544c811b99SArnd Bergmann 554c811b99SArnd Bergmann /* 564c811b99SArnd Bergmann * Core-specific peripheral registers. 574c811b99SArnd Bergmann */ 584c811b99SArnd Bergmann #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) 594c811b99SArnd Bergmann #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) 604c811b99SArnd Bergmann #define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) 614c811b99SArnd Bergmann #define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) 624c811b99SArnd Bergmann #define BRIDGE_WINS_SZ (0xA000) 634c811b99SArnd Bergmann 644c811b99SArnd Bergmann /* 654c811b99SArnd Bergmann * Register Map 664c811b99SArnd Bergmann */ 674c811b99SArnd Bergmann #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) 684c811b99SArnd Bergmann #define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) 694c811b99SArnd Bergmann #define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) 704c811b99SArnd Bergmann #define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) 714c811b99SArnd Bergmann #define DDR_WINDOW_CPU_SZ (0x20) 724c811b99SArnd Bergmann 734c811b99SArnd Bergmann #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) 744c811b99SArnd Bergmann #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) 754c811b99SArnd Bergmann #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) 764c811b99SArnd Bergmann #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) 774c811b99SArnd Bergmann #define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) 784c811b99SArnd Bergmann #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) 794c811b99SArnd Bergmann #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) 804c811b99SArnd Bergmann #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) 814c811b99SArnd Bergmann #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) 824c811b99SArnd Bergmann #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) 834c811b99SArnd Bergmann #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) 844c811b99SArnd Bergmann #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) 854c811b99SArnd Bergmann #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) 864c811b99SArnd Bergmann #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) 874c811b99SArnd Bergmann #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) 884c811b99SArnd Bergmann 894c811b99SArnd Bergmann #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) 904c811b99SArnd Bergmann #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) 914c811b99SArnd Bergmann 924c811b99SArnd Bergmann #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) 934c811b99SArnd Bergmann #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) 944c811b99SArnd Bergmann #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) 954c811b99SArnd Bergmann #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) 964c811b99SArnd Bergmann 974c811b99SArnd Bergmann #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) 984c811b99SArnd Bergmann #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) 994c811b99SArnd Bergmann #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) 1004c811b99SArnd Bergmann 1014c811b99SArnd Bergmann #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) 1024c811b99SArnd Bergmann #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) 1034c811b99SArnd Bergmann 1044c811b99SArnd Bergmann #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) 1054c811b99SArnd Bergmann #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) 1064c811b99SArnd Bergmann #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) 1074c811b99SArnd Bergmann #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) 1084c811b99SArnd Bergmann 1094c811b99SArnd Bergmann #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) 1104c811b99SArnd Bergmann 1114c811b99SArnd Bergmann /* 1124c811b99SArnd Bergmann * Supported devices and revisions. 1134c811b99SArnd Bergmann */ 1144c811b99SArnd Bergmann #define MV78X00_Z0_DEV_ID 0x6381 1154c811b99SArnd Bergmann #define MV78X00_REV_Z0 1 1164c811b99SArnd Bergmann 1174c811b99SArnd Bergmann #define MV78100_DEV_ID 0x7810 1184c811b99SArnd Bergmann #define MV78100_REV_A0 1 1194c811b99SArnd Bergmann #define MV78100_REV_A1 2 1204c811b99SArnd Bergmann 1214c811b99SArnd Bergmann #define MV78200_DEV_ID 0x7820 1224c811b99SArnd Bergmann #define MV78200_REV_A0 1 1234c811b99SArnd Bergmann 1244c811b99SArnd Bergmann #endif 125