1 /* 2 * arch/arm/mach-mv78xx0/irq.c 3 * 4 * MV78xx0 IRQ handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/irq.h> 15 #include <asm/gpio.h> 16 #include <mach/bridge-regs.h> 17 #include <plat/irq.h> 18 #include "common.h" 19 20 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 21 { 22 BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31); 23 24 orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3); 25 } 26 27 void __init mv78xx0_init_irq(void) 28 { 29 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 30 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 31 orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); 32 33 /* 34 * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask 35 * registers for core #1 are at an offset of 0x18 from those of 36 * core #0.) 37 */ 38 orion_gpio_init(0, 32, GPIO_VIRT_BASE, 39 mv78xx0_core_index() ? 0x18 : 0, 40 IRQ_MV78XX0_GPIO_START); 41 set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); 42 set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); 43 set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); 44 set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); 45 } 46