1 /* 2 * arch/arm/mach-mv78xx0/common.c 3 * 4 * Core functions for Marvell MV78xx0 SoCs 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/platform_device.h> 14 #include <linux/serial_8250.h> 15 #include <linux/mbus.h> 16 #include <linux/mv643xx_eth.h> 17 #include <linux/ata_platform.h> 18 #include <asm/mach/map.h> 19 #include <asm/mach/time.h> 20 #include <mach/mv78xx0.h> 21 #include <plat/cache-feroceon-l2.h> 22 #include <plat/ehci-orion.h> 23 #include <plat/orion_nand.h> 24 #include <plat/time.h> 25 #include "common.h" 26 27 28 /***************************************************************************** 29 * Common bits 30 ****************************************************************************/ 31 int mv78xx0_core_index(void) 32 { 33 u32 extra; 34 35 /* 36 * Read Extra Features register. 37 */ 38 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); 39 40 return !!(extra & 0x00004000); 41 } 42 43 static int get_hclk(void) 44 { 45 int hclk; 46 47 /* 48 * HCLK tick rate is configured by DEV_D[7:5] pins. 49 */ 50 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { 51 case 0: 52 hclk = 166666667; 53 break; 54 case 1: 55 hclk = 200000000; 56 break; 57 case 2: 58 hclk = 266666667; 59 break; 60 case 3: 61 hclk = 333333333; 62 break; 63 case 4: 64 hclk = 400000000; 65 break; 66 default: 67 panic("unknown HCLK PLL setting: %.8x\n", 68 readl(SAMPLE_AT_RESET_LOW)); 69 } 70 71 return hclk; 72 } 73 74 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) 75 { 76 u32 cfg; 77 78 /* 79 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 80 * PCLK/L2CLK by bits [19:14]. 81 */ 82 if (core_index == 0) { 83 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; 84 } else { 85 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; 86 } 87 88 /* 89 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK 90 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). 91 */ 92 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; 93 94 /* 95 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK 96 * ratio (1, 2, 3). 97 */ 98 *l2clk = *pclk / (((cfg >> 4) & 3) + 1); 99 } 100 101 static int get_tclk(void) 102 { 103 int tclk; 104 105 /* 106 * TCLK tick rate is configured by DEV_A[2:0] strap pins. 107 */ 108 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { 109 case 1: 110 tclk = 166666667; 111 break; 112 case 3: 113 tclk = 200000000; 114 break; 115 default: 116 panic("unknown TCLK PLL setting: %.8x\n", 117 readl(SAMPLE_AT_RESET_HIGH)); 118 } 119 120 return tclk; 121 } 122 123 124 /***************************************************************************** 125 * I/O Address Mapping 126 ****************************************************************************/ 127 static struct map_desc mv78xx0_io_desc[] __initdata = { 128 { 129 .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 130 .pfn = 0, 131 .length = MV78XX0_CORE_REGS_SIZE, 132 .type = MT_DEVICE, 133 }, { 134 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), 135 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), 136 .length = MV78XX0_PCIE_IO_SIZE * 8, 137 .type = MT_DEVICE, 138 }, { 139 .virtual = MV78XX0_REGS_VIRT_BASE, 140 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 141 .length = MV78XX0_REGS_SIZE, 142 .type = MT_DEVICE, 143 }, 144 }; 145 146 void __init mv78xx0_map_io(void) 147 { 148 unsigned long phys; 149 150 /* 151 * Map the right set of per-core registers depending on 152 * which core we are running on. 153 */ 154 if (mv78xx0_core_index() == 0) { 155 phys = MV78XX0_CORE0_REGS_PHYS_BASE; 156 } else { 157 phys = MV78XX0_CORE1_REGS_PHYS_BASE; 158 } 159 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); 160 161 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); 162 } 163 164 165 /***************************************************************************** 166 * EHCI 167 ****************************************************************************/ 168 static struct orion_ehci_data mv78xx0_ehci_data = { 169 .dram = &mv78xx0_mbus_dram_info, 170 }; 171 172 static u64 ehci_dmamask = 0xffffffffUL; 173 174 175 /***************************************************************************** 176 * EHCI0 177 ****************************************************************************/ 178 static struct resource mv78xx0_ehci0_resources[] = { 179 { 180 .start = USB0_PHYS_BASE, 181 .end = USB0_PHYS_BASE + 0x0fff, 182 .flags = IORESOURCE_MEM, 183 }, { 184 .start = IRQ_MV78XX0_USB_0, 185 .end = IRQ_MV78XX0_USB_0, 186 .flags = IORESOURCE_IRQ, 187 }, 188 }; 189 190 static struct platform_device mv78xx0_ehci0 = { 191 .name = "orion-ehci", 192 .id = 0, 193 .dev = { 194 .dma_mask = &ehci_dmamask, 195 .coherent_dma_mask = 0xffffffff, 196 .platform_data = &mv78xx0_ehci_data, 197 }, 198 .resource = mv78xx0_ehci0_resources, 199 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), 200 }; 201 202 void __init mv78xx0_ehci0_init(void) 203 { 204 platform_device_register(&mv78xx0_ehci0); 205 } 206 207 208 /***************************************************************************** 209 * EHCI1 210 ****************************************************************************/ 211 static struct resource mv78xx0_ehci1_resources[] = { 212 { 213 .start = USB1_PHYS_BASE, 214 .end = USB1_PHYS_BASE + 0x0fff, 215 .flags = IORESOURCE_MEM, 216 }, { 217 .start = IRQ_MV78XX0_USB_1, 218 .end = IRQ_MV78XX0_USB_1, 219 .flags = IORESOURCE_IRQ, 220 }, 221 }; 222 223 static struct platform_device mv78xx0_ehci1 = { 224 .name = "orion-ehci", 225 .id = 1, 226 .dev = { 227 .dma_mask = &ehci_dmamask, 228 .coherent_dma_mask = 0xffffffff, 229 .platform_data = &mv78xx0_ehci_data, 230 }, 231 .resource = mv78xx0_ehci1_resources, 232 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), 233 }; 234 235 void __init mv78xx0_ehci1_init(void) 236 { 237 platform_device_register(&mv78xx0_ehci1); 238 } 239 240 241 /***************************************************************************** 242 * EHCI2 243 ****************************************************************************/ 244 static struct resource mv78xx0_ehci2_resources[] = { 245 { 246 .start = USB2_PHYS_BASE, 247 .end = USB2_PHYS_BASE + 0x0fff, 248 .flags = IORESOURCE_MEM, 249 }, { 250 .start = IRQ_MV78XX0_USB_2, 251 .end = IRQ_MV78XX0_USB_2, 252 .flags = IORESOURCE_IRQ, 253 }, 254 }; 255 256 static struct platform_device mv78xx0_ehci2 = { 257 .name = "orion-ehci", 258 .id = 2, 259 .dev = { 260 .dma_mask = &ehci_dmamask, 261 .coherent_dma_mask = 0xffffffff, 262 .platform_data = &mv78xx0_ehci_data, 263 }, 264 .resource = mv78xx0_ehci2_resources, 265 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), 266 }; 267 268 void __init mv78xx0_ehci2_init(void) 269 { 270 platform_device_register(&mv78xx0_ehci2); 271 } 272 273 274 /***************************************************************************** 275 * GE00 276 ****************************************************************************/ 277 struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = { 278 .t_clk = 0, 279 .dram = &mv78xx0_mbus_dram_info, 280 }; 281 282 static struct resource mv78xx0_ge00_shared_resources[] = { 283 { 284 .name = "ge00 base", 285 .start = GE00_PHYS_BASE + 0x2000, 286 .end = GE00_PHYS_BASE + 0x3fff, 287 .flags = IORESOURCE_MEM, 288 }, { 289 .name = "ge err irq", 290 .start = IRQ_MV78XX0_GE_ERR, 291 .end = IRQ_MV78XX0_GE_ERR, 292 .flags = IORESOURCE_IRQ, 293 }, 294 }; 295 296 static struct platform_device mv78xx0_ge00_shared = { 297 .name = MV643XX_ETH_SHARED_NAME, 298 .id = 0, 299 .dev = { 300 .platform_data = &mv78xx0_ge00_shared_data, 301 }, 302 .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources), 303 .resource = mv78xx0_ge00_shared_resources, 304 }; 305 306 static struct resource mv78xx0_ge00_resources[] = { 307 { 308 .name = "ge00 irq", 309 .start = IRQ_MV78XX0_GE00_SUM, 310 .end = IRQ_MV78XX0_GE00_SUM, 311 .flags = IORESOURCE_IRQ, 312 }, 313 }; 314 315 static struct platform_device mv78xx0_ge00 = { 316 .name = MV643XX_ETH_NAME, 317 .id = 0, 318 .num_resources = 1, 319 .resource = mv78xx0_ge00_resources, 320 }; 321 322 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 323 { 324 eth_data->shared = &mv78xx0_ge00_shared; 325 mv78xx0_ge00.dev.platform_data = eth_data; 326 327 platform_device_register(&mv78xx0_ge00_shared); 328 platform_device_register(&mv78xx0_ge00); 329 } 330 331 332 /***************************************************************************** 333 * GE01 334 ****************************************************************************/ 335 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = { 336 .t_clk = 0, 337 .dram = &mv78xx0_mbus_dram_info, 338 .shared_smi = &mv78xx0_ge00_shared, 339 }; 340 341 static struct resource mv78xx0_ge01_shared_resources[] = { 342 { 343 .name = "ge01 base", 344 .start = GE01_PHYS_BASE + 0x2000, 345 .end = GE01_PHYS_BASE + 0x3fff, 346 .flags = IORESOURCE_MEM, 347 }, 348 }; 349 350 static struct platform_device mv78xx0_ge01_shared = { 351 .name = MV643XX_ETH_SHARED_NAME, 352 .id = 1, 353 .dev = { 354 .platform_data = &mv78xx0_ge01_shared_data, 355 }, 356 .num_resources = 1, 357 .resource = mv78xx0_ge01_shared_resources, 358 }; 359 360 static struct resource mv78xx0_ge01_resources[] = { 361 { 362 .name = "ge01 irq", 363 .start = IRQ_MV78XX0_GE01_SUM, 364 .end = IRQ_MV78XX0_GE01_SUM, 365 .flags = IORESOURCE_IRQ, 366 }, 367 }; 368 369 static struct platform_device mv78xx0_ge01 = { 370 .name = MV643XX_ETH_NAME, 371 .id = 1, 372 .num_resources = 1, 373 .resource = mv78xx0_ge01_resources, 374 }; 375 376 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 377 { 378 eth_data->shared = &mv78xx0_ge01_shared; 379 mv78xx0_ge01.dev.platform_data = eth_data; 380 381 platform_device_register(&mv78xx0_ge01_shared); 382 platform_device_register(&mv78xx0_ge01); 383 } 384 385 386 /***************************************************************************** 387 * GE10 388 ****************************************************************************/ 389 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = { 390 .t_clk = 0, 391 .dram = &mv78xx0_mbus_dram_info, 392 .shared_smi = &mv78xx0_ge00_shared, 393 }; 394 395 static struct resource mv78xx0_ge10_shared_resources[] = { 396 { 397 .name = "ge10 base", 398 .start = GE10_PHYS_BASE + 0x2000, 399 .end = GE10_PHYS_BASE + 0x3fff, 400 .flags = IORESOURCE_MEM, 401 }, 402 }; 403 404 static struct platform_device mv78xx0_ge10_shared = { 405 .name = MV643XX_ETH_SHARED_NAME, 406 .id = 2, 407 .dev = { 408 .platform_data = &mv78xx0_ge10_shared_data, 409 }, 410 .num_resources = 1, 411 .resource = mv78xx0_ge10_shared_resources, 412 }; 413 414 static struct resource mv78xx0_ge10_resources[] = { 415 { 416 .name = "ge10 irq", 417 .start = IRQ_MV78XX0_GE10_SUM, 418 .end = IRQ_MV78XX0_GE10_SUM, 419 .flags = IORESOURCE_IRQ, 420 }, 421 }; 422 423 static struct platform_device mv78xx0_ge10 = { 424 .name = MV643XX_ETH_NAME, 425 .id = 2, 426 .num_resources = 1, 427 .resource = mv78xx0_ge10_resources, 428 }; 429 430 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 431 { 432 eth_data->shared = &mv78xx0_ge10_shared; 433 mv78xx0_ge10.dev.platform_data = eth_data; 434 435 platform_device_register(&mv78xx0_ge10_shared); 436 platform_device_register(&mv78xx0_ge10); 437 } 438 439 440 /***************************************************************************** 441 * GE11 442 ****************************************************************************/ 443 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = { 444 .t_clk = 0, 445 .dram = &mv78xx0_mbus_dram_info, 446 .shared_smi = &mv78xx0_ge00_shared, 447 }; 448 449 static struct resource mv78xx0_ge11_shared_resources[] = { 450 { 451 .name = "ge11 base", 452 .start = GE11_PHYS_BASE + 0x2000, 453 .end = GE11_PHYS_BASE + 0x3fff, 454 .flags = IORESOURCE_MEM, 455 }, 456 }; 457 458 static struct platform_device mv78xx0_ge11_shared = { 459 .name = MV643XX_ETH_SHARED_NAME, 460 .id = 3, 461 .dev = { 462 .platform_data = &mv78xx0_ge11_shared_data, 463 }, 464 .num_resources = 1, 465 .resource = mv78xx0_ge11_shared_resources, 466 }; 467 468 static struct resource mv78xx0_ge11_resources[] = { 469 { 470 .name = "ge11 irq", 471 .start = IRQ_MV78XX0_GE11_SUM, 472 .end = IRQ_MV78XX0_GE11_SUM, 473 .flags = IORESOURCE_IRQ, 474 }, 475 }; 476 477 static struct platform_device mv78xx0_ge11 = { 478 .name = MV643XX_ETH_NAME, 479 .id = 3, 480 .num_resources = 1, 481 .resource = mv78xx0_ge11_resources, 482 }; 483 484 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 485 { 486 eth_data->shared = &mv78xx0_ge11_shared; 487 mv78xx0_ge11.dev.platform_data = eth_data; 488 489 platform_device_register(&mv78xx0_ge11_shared); 490 platform_device_register(&mv78xx0_ge11); 491 } 492 493 494 /***************************************************************************** 495 * SATA 496 ****************************************************************************/ 497 static struct resource mv78xx0_sata_resources[] = { 498 { 499 .name = "sata base", 500 .start = SATA_PHYS_BASE, 501 .end = SATA_PHYS_BASE + 0x5000 - 1, 502 .flags = IORESOURCE_MEM, 503 }, { 504 .name = "sata irq", 505 .start = IRQ_MV78XX0_SATA, 506 .end = IRQ_MV78XX0_SATA, 507 .flags = IORESOURCE_IRQ, 508 }, 509 }; 510 511 static struct platform_device mv78xx0_sata = { 512 .name = "sata_mv", 513 .id = 0, 514 .dev = { 515 .coherent_dma_mask = 0xffffffff, 516 }, 517 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), 518 .resource = mv78xx0_sata_resources, 519 }; 520 521 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 522 { 523 sata_data->dram = &mv78xx0_mbus_dram_info; 524 mv78xx0_sata.dev.platform_data = sata_data; 525 platform_device_register(&mv78xx0_sata); 526 } 527 528 529 /***************************************************************************** 530 * UART0 531 ****************************************************************************/ 532 static struct plat_serial8250_port mv78xx0_uart0_data[] = { 533 { 534 .mapbase = UART0_PHYS_BASE, 535 .membase = (char *)UART0_VIRT_BASE, 536 .irq = IRQ_MV78XX0_UART_0, 537 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 538 .iotype = UPIO_MEM, 539 .regshift = 2, 540 .uartclk = 0, 541 }, { 542 }, 543 }; 544 545 static struct resource mv78xx0_uart0_resources[] = { 546 { 547 .start = UART0_PHYS_BASE, 548 .end = UART0_PHYS_BASE + 0xff, 549 .flags = IORESOURCE_MEM, 550 }, { 551 .start = IRQ_MV78XX0_UART_0, 552 .end = IRQ_MV78XX0_UART_0, 553 .flags = IORESOURCE_IRQ, 554 }, 555 }; 556 557 static struct platform_device mv78xx0_uart0 = { 558 .name = "serial8250", 559 .id = 0, 560 .dev = { 561 .platform_data = mv78xx0_uart0_data, 562 }, 563 .resource = mv78xx0_uart0_resources, 564 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources), 565 }; 566 567 void __init mv78xx0_uart0_init(void) 568 { 569 platform_device_register(&mv78xx0_uart0); 570 } 571 572 573 /***************************************************************************** 574 * UART1 575 ****************************************************************************/ 576 static struct plat_serial8250_port mv78xx0_uart1_data[] = { 577 { 578 .mapbase = UART1_PHYS_BASE, 579 .membase = (char *)UART1_VIRT_BASE, 580 .irq = IRQ_MV78XX0_UART_1, 581 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 582 .iotype = UPIO_MEM, 583 .regshift = 2, 584 .uartclk = 0, 585 }, { 586 }, 587 }; 588 589 static struct resource mv78xx0_uart1_resources[] = { 590 { 591 .start = UART1_PHYS_BASE, 592 .end = UART1_PHYS_BASE + 0xff, 593 .flags = IORESOURCE_MEM, 594 }, { 595 .start = IRQ_MV78XX0_UART_1, 596 .end = IRQ_MV78XX0_UART_1, 597 .flags = IORESOURCE_IRQ, 598 }, 599 }; 600 601 static struct platform_device mv78xx0_uart1 = { 602 .name = "serial8250", 603 .id = 1, 604 .dev = { 605 .platform_data = mv78xx0_uart1_data, 606 }, 607 .resource = mv78xx0_uart1_resources, 608 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources), 609 }; 610 611 void __init mv78xx0_uart1_init(void) 612 { 613 platform_device_register(&mv78xx0_uart1); 614 } 615 616 617 /***************************************************************************** 618 * UART2 619 ****************************************************************************/ 620 static struct plat_serial8250_port mv78xx0_uart2_data[] = { 621 { 622 .mapbase = UART2_PHYS_BASE, 623 .membase = (char *)UART2_VIRT_BASE, 624 .irq = IRQ_MV78XX0_UART_2, 625 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 626 .iotype = UPIO_MEM, 627 .regshift = 2, 628 .uartclk = 0, 629 }, { 630 }, 631 }; 632 633 static struct resource mv78xx0_uart2_resources[] = { 634 { 635 .start = UART2_PHYS_BASE, 636 .end = UART2_PHYS_BASE + 0xff, 637 .flags = IORESOURCE_MEM, 638 }, { 639 .start = IRQ_MV78XX0_UART_2, 640 .end = IRQ_MV78XX0_UART_2, 641 .flags = IORESOURCE_IRQ, 642 }, 643 }; 644 645 static struct platform_device mv78xx0_uart2 = { 646 .name = "serial8250", 647 .id = 2, 648 .dev = { 649 .platform_data = mv78xx0_uart2_data, 650 }, 651 .resource = mv78xx0_uart2_resources, 652 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources), 653 }; 654 655 void __init mv78xx0_uart2_init(void) 656 { 657 platform_device_register(&mv78xx0_uart2); 658 } 659 660 661 /***************************************************************************** 662 * UART3 663 ****************************************************************************/ 664 static struct plat_serial8250_port mv78xx0_uart3_data[] = { 665 { 666 .mapbase = UART3_PHYS_BASE, 667 .membase = (char *)UART3_VIRT_BASE, 668 .irq = IRQ_MV78XX0_UART_3, 669 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 670 .iotype = UPIO_MEM, 671 .regshift = 2, 672 .uartclk = 0, 673 }, { 674 }, 675 }; 676 677 static struct resource mv78xx0_uart3_resources[] = { 678 { 679 .start = UART3_PHYS_BASE, 680 .end = UART3_PHYS_BASE + 0xff, 681 .flags = IORESOURCE_MEM, 682 }, { 683 .start = IRQ_MV78XX0_UART_3, 684 .end = IRQ_MV78XX0_UART_3, 685 .flags = IORESOURCE_IRQ, 686 }, 687 }; 688 689 static struct platform_device mv78xx0_uart3 = { 690 .name = "serial8250", 691 .id = 3, 692 .dev = { 693 .platform_data = mv78xx0_uart3_data, 694 }, 695 .resource = mv78xx0_uart3_resources, 696 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources), 697 }; 698 699 void __init mv78xx0_uart3_init(void) 700 { 701 platform_device_register(&mv78xx0_uart3); 702 } 703 704 705 /***************************************************************************** 706 * Time handling 707 ****************************************************************************/ 708 static void mv78xx0_timer_init(void) 709 { 710 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk()); 711 } 712 713 struct sys_timer mv78xx0_timer = { 714 .init = mv78xx0_timer_init, 715 }; 716 717 718 /***************************************************************************** 719 * General 720 ****************************************************************************/ 721 static int __init is_l2_writethrough(void) 722 { 723 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); 724 } 725 726 void __init mv78xx0_init(void) 727 { 728 int core_index; 729 int hclk; 730 int pclk; 731 int l2clk; 732 int tclk; 733 734 core_index = mv78xx0_core_index(); 735 hclk = get_hclk(); 736 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); 737 tclk = get_tclk(); 738 739 printk(KERN_INFO "MV78xx0 core #%d, ", core_index); 740 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); 741 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); 742 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 743 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); 744 745 mv78xx0_setup_cpu_mbus(); 746 747 #ifdef CONFIG_CACHE_FEROCEON_L2 748 feroceon_l2_init(is_l2_writethrough()); 749 #endif 750 751 mv78xx0_ge00_shared_data.t_clk = tclk; 752 mv78xx0_ge01_shared_data.t_clk = tclk; 753 mv78xx0_ge10_shared_data.t_clk = tclk; 754 mv78xx0_ge11_shared_data.t_clk = tclk; 755 mv78xx0_uart0_data[0].uartclk = tclk; 756 mv78xx0_uart1_data[0].uartclk = tclk; 757 mv78xx0_uart2_data[0].uartclk = tclk; 758 mv78xx0_uart3_data[0].uartclk = tclk; 759 } 760