1 /* 2 * arch/arm/mach-mv78xx0/common.c 3 * 4 * Core functions for Marvell MV78xx0 SoCs 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/platform_device.h> 14 #include <linux/serial_8250.h> 15 #include <linux/ata_platform.h> 16 #include <linux/clk-provider.h> 17 #include <linux/ethtool.h> 18 #include <asm/mach/map.h> 19 #include <asm/mach/time.h> 20 #include <mach/mv78xx0.h> 21 #include <mach/bridge-regs.h> 22 #include <plat/cache-feroceon-l2.h> 23 #include <plat/ehci-orion.h> 24 #include <plat/orion_nand.h> 25 #include <plat/time.h> 26 #include <plat/common.h> 27 #include <plat/addr-map.h> 28 #include "common.h" 29 30 static int get_tclk(void); 31 32 /***************************************************************************** 33 * Common bits 34 ****************************************************************************/ 35 int mv78xx0_core_index(void) 36 { 37 u32 extra; 38 39 /* 40 * Read Extra Features register. 41 */ 42 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); 43 44 return !!(extra & 0x00004000); 45 } 46 47 static int get_hclk(void) 48 { 49 int hclk; 50 51 /* 52 * HCLK tick rate is configured by DEV_D[7:5] pins. 53 */ 54 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { 55 case 0: 56 hclk = 166666667; 57 break; 58 case 1: 59 hclk = 200000000; 60 break; 61 case 2: 62 hclk = 266666667; 63 break; 64 case 3: 65 hclk = 333333333; 66 break; 67 case 4: 68 hclk = 400000000; 69 break; 70 default: 71 panic("unknown HCLK PLL setting: %.8x\n", 72 readl(SAMPLE_AT_RESET_LOW)); 73 } 74 75 return hclk; 76 } 77 78 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) 79 { 80 u32 cfg; 81 82 /* 83 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 84 * PCLK/L2CLK by bits [19:14]. 85 */ 86 if (core_index == 0) { 87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; 88 } else { 89 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; 90 } 91 92 /* 93 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK 94 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). 95 */ 96 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; 97 98 /* 99 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK 100 * ratio (1, 2, 3). 101 */ 102 *l2clk = *pclk / (((cfg >> 4) & 3) + 1); 103 } 104 105 static int get_tclk(void) 106 { 107 int tclk_freq; 108 109 /* 110 * TCLK tick rate is configured by DEV_A[2:0] strap pins. 111 */ 112 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { 113 case 1: 114 tclk_freq = 166666667; 115 break; 116 case 3: 117 tclk_freq = 200000000; 118 break; 119 default: 120 panic("unknown TCLK PLL setting: %.8x\n", 121 readl(SAMPLE_AT_RESET_HIGH)); 122 } 123 124 return tclk_freq; 125 } 126 127 128 /***************************************************************************** 129 * I/O Address Mapping 130 ****************************************************************************/ 131 static struct map_desc mv78xx0_io_desc[] __initdata = { 132 { 133 .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 134 .pfn = 0, 135 .length = MV78XX0_CORE_REGS_SIZE, 136 .type = MT_DEVICE, 137 }, { 138 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), 139 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), 140 .length = MV78XX0_PCIE_IO_SIZE * 8, 141 .type = MT_DEVICE, 142 }, { 143 .virtual = MV78XX0_REGS_VIRT_BASE, 144 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 145 .length = MV78XX0_REGS_SIZE, 146 .type = MT_DEVICE, 147 }, 148 }; 149 150 void __init mv78xx0_map_io(void) 151 { 152 unsigned long phys; 153 154 /* 155 * Map the right set of per-core registers depending on 156 * which core we are running on. 157 */ 158 if (mv78xx0_core_index() == 0) { 159 phys = MV78XX0_CORE0_REGS_PHYS_BASE; 160 } else { 161 phys = MV78XX0_CORE1_REGS_PHYS_BASE; 162 } 163 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); 164 165 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); 166 } 167 168 169 /***************************************************************************** 170 * CLK tree 171 ****************************************************************************/ 172 static struct clk *tclk; 173 174 static void __init clk_init(void) 175 { 176 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, 177 get_tclk()); 178 } 179 180 /***************************************************************************** 181 * EHCI 182 ****************************************************************************/ 183 void __init mv78xx0_ehci0_init(void) 184 { 185 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); 186 } 187 188 189 /***************************************************************************** 190 * EHCI1 191 ****************************************************************************/ 192 void __init mv78xx0_ehci1_init(void) 193 { 194 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); 195 } 196 197 198 /***************************************************************************** 199 * EHCI2 200 ****************************************************************************/ 201 void __init mv78xx0_ehci2_init(void) 202 { 203 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); 204 } 205 206 207 /***************************************************************************** 208 * GE00 209 ****************************************************************************/ 210 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 211 { 212 orion_ge00_init(eth_data, 213 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 214 IRQ_MV78XX0_GE_ERR, get_tclk()); 215 } 216 217 218 /***************************************************************************** 219 * GE01 220 ****************************************************************************/ 221 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 222 { 223 orion_ge01_init(eth_data, 224 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 225 NO_IRQ, get_tclk()); 226 } 227 228 229 /***************************************************************************** 230 * GE10 231 ****************************************************************************/ 232 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 233 { 234 u32 dev, rev; 235 236 /* 237 * On the Z0, ge10 and ge11 are internally connected back 238 * to back, and not brought out. 239 */ 240 mv78xx0_pcie_id(&dev, &rev); 241 if (dev == MV78X00_Z0_DEV_ID) { 242 eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 243 eth_data->speed = SPEED_1000; 244 eth_data->duplex = DUPLEX_FULL; 245 } 246 247 orion_ge10_init(eth_data, 248 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 249 NO_IRQ, get_tclk()); 250 } 251 252 253 /***************************************************************************** 254 * GE11 255 ****************************************************************************/ 256 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 257 { 258 u32 dev, rev; 259 260 /* 261 * On the Z0, ge10 and ge11 are internally connected back 262 * to back, and not brought out. 263 */ 264 mv78xx0_pcie_id(&dev, &rev); 265 if (dev == MV78X00_Z0_DEV_ID) { 266 eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 267 eth_data->speed = SPEED_1000; 268 eth_data->duplex = DUPLEX_FULL; 269 } 270 271 orion_ge11_init(eth_data, 272 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 273 NO_IRQ, get_tclk()); 274 } 275 276 /***************************************************************************** 277 * I2C 278 ****************************************************************************/ 279 void __init mv78xx0_i2c_init(void) 280 { 281 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); 282 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); 283 } 284 285 /***************************************************************************** 286 * SATA 287 ****************************************************************************/ 288 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 289 { 290 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); 291 } 292 293 294 /***************************************************************************** 295 * UART0 296 ****************************************************************************/ 297 void __init mv78xx0_uart0_init(void) 298 { 299 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 300 IRQ_MV78XX0_UART_0, get_tclk()); 301 } 302 303 304 /***************************************************************************** 305 * UART1 306 ****************************************************************************/ 307 void __init mv78xx0_uart1_init(void) 308 { 309 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 310 IRQ_MV78XX0_UART_1, get_tclk()); 311 } 312 313 314 /***************************************************************************** 315 * UART2 316 ****************************************************************************/ 317 void __init mv78xx0_uart2_init(void) 318 { 319 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, 320 IRQ_MV78XX0_UART_2, get_tclk()); 321 } 322 323 /***************************************************************************** 324 * UART3 325 ****************************************************************************/ 326 void __init mv78xx0_uart3_init(void) 327 { 328 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, 329 IRQ_MV78XX0_UART_3, get_tclk()); 330 } 331 332 /***************************************************************************** 333 * Time handling 334 ****************************************************************************/ 335 void __init mv78xx0_init_early(void) 336 { 337 orion_time_set_base(TIMER_VIRT_BASE); 338 } 339 340 static void mv78xx0_timer_init(void) 341 { 342 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 343 IRQ_MV78XX0_TIMER_1, get_tclk()); 344 } 345 346 struct sys_timer mv78xx0_timer = { 347 .init = mv78xx0_timer_init, 348 }; 349 350 351 /***************************************************************************** 352 * General 353 ****************************************************************************/ 354 static char * __init mv78xx0_id(void) 355 { 356 u32 dev, rev; 357 358 mv78xx0_pcie_id(&dev, &rev); 359 360 if (dev == MV78X00_Z0_DEV_ID) { 361 if (rev == MV78X00_REV_Z0) 362 return "MV78X00-Z0"; 363 else 364 return "MV78X00-Rev-Unsupported"; 365 } else if (dev == MV78100_DEV_ID) { 366 if (rev == MV78100_REV_A0) 367 return "MV78100-A0"; 368 else if (rev == MV78100_REV_A1) 369 return "MV78100-A1"; 370 else 371 return "MV78100-Rev-Unsupported"; 372 } else if (dev == MV78200_DEV_ID) { 373 if (rev == MV78100_REV_A0) 374 return "MV78200-A0"; 375 else 376 return "MV78200-Rev-Unsupported"; 377 } else { 378 return "Device-Unknown"; 379 } 380 } 381 382 static int __init is_l2_writethrough(void) 383 { 384 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); 385 } 386 387 void __init mv78xx0_init(void) 388 { 389 int core_index; 390 int hclk; 391 int pclk; 392 int l2clk; 393 394 core_index = mv78xx0_core_index(); 395 hclk = get_hclk(); 396 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); 397 398 printk(KERN_INFO "%s ", mv78xx0_id()); 399 printk("core #%d, ", core_index); 400 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); 401 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); 402 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 403 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); 404 405 mv78xx0_setup_cpu_mbus(); 406 407 #ifdef CONFIG_CACHE_FEROCEON_L2 408 feroceon_l2_init(is_l2_writethrough()); 409 #endif 410 411 /* Setup root of clk tree */ 412 clk_init(); 413 } 414 415 void mv78xx0_restart(char mode, const char *cmd) 416 { 417 /* 418 * Enable soft reset to assert RSTOUTn. 419 */ 420 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 421 422 /* 423 * Assert soft reset. 424 */ 425 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 426 427 while (1) 428 ; 429 } 430