1794d15b2SStanislav Samsonov /* 2794d15b2SStanislav Samsonov * arch/arm/mach-mv78xx0/common.c 3794d15b2SStanislav Samsonov * 4794d15b2SStanislav Samsonov * Core functions for Marvell MV78xx0 SoCs 5794d15b2SStanislav Samsonov * 6794d15b2SStanislav Samsonov * This file is licensed under the terms of the GNU General Public 7794d15b2SStanislav Samsonov * License version 2. This program is licensed "as is" without any 8794d15b2SStanislav Samsonov * warranty of any kind, whether express or implied. 9794d15b2SStanislav Samsonov */ 10794d15b2SStanislav Samsonov 11794d15b2SStanislav Samsonov #include <linux/kernel.h> 12794d15b2SStanislav Samsonov #include <linux/init.h> 13794d15b2SStanislav Samsonov #include <linux/platform_device.h> 14794d15b2SStanislav Samsonov #include <linux/serial_8250.h> 15794d15b2SStanislav Samsonov #include <linux/ata_platform.h> 16712424fdSLennert Buytenhek #include <linux/ethtool.h> 17794d15b2SStanislav Samsonov #include <asm/mach/map.h> 18794d15b2SStanislav Samsonov #include <asm/mach/time.h> 19a09e64fbSRussell King #include <mach/mv78xx0.h> 20fdd8b079SNicolas Pitre #include <mach/bridge-regs.h> 216f088f1dSLennert Buytenhek #include <plat/cache-feroceon-l2.h> 226f088f1dSLennert Buytenhek #include <plat/orion_nand.h> 236f088f1dSLennert Buytenhek #include <plat/time.h> 2428a2b450SAndrew Lunn #include <plat/common.h> 2545173d5eSAndrew Lunn #include <plat/addr-map.h> 26794d15b2SStanislav Samsonov #include "common.h" 27794d15b2SStanislav Samsonov 2828a2b450SAndrew Lunn static int get_tclk(void); 29794d15b2SStanislav Samsonov 30794d15b2SStanislav Samsonov /***************************************************************************** 31794d15b2SStanislav Samsonov * Common bits 32794d15b2SStanislav Samsonov ****************************************************************************/ 33794d15b2SStanislav Samsonov int mv78xx0_core_index(void) 34794d15b2SStanislav Samsonov { 35794d15b2SStanislav Samsonov u32 extra; 36794d15b2SStanislav Samsonov 37794d15b2SStanislav Samsonov /* 38794d15b2SStanislav Samsonov * Read Extra Features register. 39794d15b2SStanislav Samsonov */ 40794d15b2SStanislav Samsonov __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); 41794d15b2SStanislav Samsonov 42794d15b2SStanislav Samsonov return !!(extra & 0x00004000); 43794d15b2SStanislav Samsonov } 44794d15b2SStanislav Samsonov 45794d15b2SStanislav Samsonov static int get_hclk(void) 46794d15b2SStanislav Samsonov { 47794d15b2SStanislav Samsonov int hclk; 48794d15b2SStanislav Samsonov 49794d15b2SStanislav Samsonov /* 50794d15b2SStanislav Samsonov * HCLK tick rate is configured by DEV_D[7:5] pins. 51794d15b2SStanislav Samsonov */ 52794d15b2SStanislav Samsonov switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { 53794d15b2SStanislav Samsonov case 0: 54794d15b2SStanislav Samsonov hclk = 166666667; 55794d15b2SStanislav Samsonov break; 56794d15b2SStanislav Samsonov case 1: 57794d15b2SStanislav Samsonov hclk = 200000000; 58794d15b2SStanislav Samsonov break; 59794d15b2SStanislav Samsonov case 2: 60794d15b2SStanislav Samsonov hclk = 266666667; 61794d15b2SStanislav Samsonov break; 62794d15b2SStanislav Samsonov case 3: 63794d15b2SStanislav Samsonov hclk = 333333333; 64794d15b2SStanislav Samsonov break; 65794d15b2SStanislav Samsonov case 4: 66794d15b2SStanislav Samsonov hclk = 400000000; 67794d15b2SStanislav Samsonov break; 68794d15b2SStanislav Samsonov default: 69794d15b2SStanislav Samsonov panic("unknown HCLK PLL setting: %.8x\n", 70794d15b2SStanislav Samsonov readl(SAMPLE_AT_RESET_LOW)); 71794d15b2SStanislav Samsonov } 72794d15b2SStanislav Samsonov 73794d15b2SStanislav Samsonov return hclk; 74794d15b2SStanislav Samsonov } 75794d15b2SStanislav Samsonov 76794d15b2SStanislav Samsonov static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) 77794d15b2SStanislav Samsonov { 78794d15b2SStanislav Samsonov u32 cfg; 79794d15b2SStanislav Samsonov 80794d15b2SStanislav Samsonov /* 81794d15b2SStanislav Samsonov * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 82794d15b2SStanislav Samsonov * PCLK/L2CLK by bits [19:14]. 83794d15b2SStanislav Samsonov */ 84794d15b2SStanislav Samsonov if (core_index == 0) { 85794d15b2SStanislav Samsonov cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; 86794d15b2SStanislav Samsonov } else { 87794d15b2SStanislav Samsonov cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; 88794d15b2SStanislav Samsonov } 89794d15b2SStanislav Samsonov 90794d15b2SStanislav Samsonov /* 91794d15b2SStanislav Samsonov * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK 92794d15b2SStanislav Samsonov * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). 93794d15b2SStanislav Samsonov */ 94794d15b2SStanislav Samsonov *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; 95794d15b2SStanislav Samsonov 96794d15b2SStanislav Samsonov /* 97794d15b2SStanislav Samsonov * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK 98794d15b2SStanislav Samsonov * ratio (1, 2, 3). 99794d15b2SStanislav Samsonov */ 100794d15b2SStanislav Samsonov *l2clk = *pclk / (((cfg >> 4) & 3) + 1); 101794d15b2SStanislav Samsonov } 102794d15b2SStanislav Samsonov 103794d15b2SStanislav Samsonov static int get_tclk(void) 104794d15b2SStanislav Samsonov { 105794d15b2SStanislav Samsonov int tclk; 106794d15b2SStanislav Samsonov 107794d15b2SStanislav Samsonov /* 108794d15b2SStanislav Samsonov * TCLK tick rate is configured by DEV_A[2:0] strap pins. 109794d15b2SStanislav Samsonov */ 110794d15b2SStanislav Samsonov switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { 111794d15b2SStanislav Samsonov case 1: 112794d15b2SStanislav Samsonov tclk = 166666667; 113794d15b2SStanislav Samsonov break; 114794d15b2SStanislav Samsonov case 3: 115794d15b2SStanislav Samsonov tclk = 200000000; 116794d15b2SStanislav Samsonov break; 117794d15b2SStanislav Samsonov default: 118794d15b2SStanislav Samsonov panic("unknown TCLK PLL setting: %.8x\n", 119794d15b2SStanislav Samsonov readl(SAMPLE_AT_RESET_HIGH)); 120794d15b2SStanislav Samsonov } 121794d15b2SStanislav Samsonov 122794d15b2SStanislav Samsonov return tclk; 123794d15b2SStanislav Samsonov } 124794d15b2SStanislav Samsonov 125794d15b2SStanislav Samsonov 126794d15b2SStanislav Samsonov /***************************************************************************** 127794d15b2SStanislav Samsonov * I/O Address Mapping 128794d15b2SStanislav Samsonov ****************************************************************************/ 129794d15b2SStanislav Samsonov static struct map_desc mv78xx0_io_desc[] __initdata = { 130794d15b2SStanislav Samsonov { 131794d15b2SStanislav Samsonov .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 132794d15b2SStanislav Samsonov .pfn = 0, 133794d15b2SStanislav Samsonov .length = MV78XX0_CORE_REGS_SIZE, 134794d15b2SStanislav Samsonov .type = MT_DEVICE, 135794d15b2SStanislav Samsonov }, { 136794d15b2SStanislav Samsonov .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), 137794d15b2SStanislav Samsonov .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), 138794d15b2SStanislav Samsonov .length = MV78XX0_PCIE_IO_SIZE * 8, 139794d15b2SStanislav Samsonov .type = MT_DEVICE, 140794d15b2SStanislav Samsonov }, { 141794d15b2SStanislav Samsonov .virtual = MV78XX0_REGS_VIRT_BASE, 142794d15b2SStanislav Samsonov .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 143794d15b2SStanislav Samsonov .length = MV78XX0_REGS_SIZE, 144794d15b2SStanislav Samsonov .type = MT_DEVICE, 145794d15b2SStanislav Samsonov }, 146794d15b2SStanislav Samsonov }; 147794d15b2SStanislav Samsonov 148794d15b2SStanislav Samsonov void __init mv78xx0_map_io(void) 149794d15b2SStanislav Samsonov { 150794d15b2SStanislav Samsonov unsigned long phys; 151794d15b2SStanislav Samsonov 152794d15b2SStanislav Samsonov /* 153794d15b2SStanislav Samsonov * Map the right set of per-core registers depending on 154794d15b2SStanislav Samsonov * which core we are running on. 155794d15b2SStanislav Samsonov */ 156794d15b2SStanislav Samsonov if (mv78xx0_core_index() == 0) { 157794d15b2SStanislav Samsonov phys = MV78XX0_CORE0_REGS_PHYS_BASE; 158794d15b2SStanislav Samsonov } else { 159794d15b2SStanislav Samsonov phys = MV78XX0_CORE1_REGS_PHYS_BASE; 160794d15b2SStanislav Samsonov } 161794d15b2SStanislav Samsonov mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); 162794d15b2SStanislav Samsonov 163794d15b2SStanislav Samsonov iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); 164794d15b2SStanislav Samsonov } 165794d15b2SStanislav Samsonov 166794d15b2SStanislav Samsonov 167794d15b2SStanislav Samsonov /***************************************************************************** 168794d15b2SStanislav Samsonov * EHCI 169794d15b2SStanislav Samsonov ****************************************************************************/ 170794d15b2SStanislav Samsonov void __init mv78xx0_ehci0_init(void) 171794d15b2SStanislav Samsonov { 172db33f4deSAndrew Lunn orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 173794d15b2SStanislav Samsonov } 174794d15b2SStanislav Samsonov 175794d15b2SStanislav Samsonov 176794d15b2SStanislav Samsonov /***************************************************************************** 177794d15b2SStanislav Samsonov * EHCI1 178794d15b2SStanislav Samsonov ****************************************************************************/ 179794d15b2SStanislav Samsonov void __init mv78xx0_ehci1_init(void) 180794d15b2SStanislav Samsonov { 181db33f4deSAndrew Lunn orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); 182794d15b2SStanislav Samsonov } 183794d15b2SStanislav Samsonov 184794d15b2SStanislav Samsonov 185794d15b2SStanislav Samsonov /***************************************************************************** 186794d15b2SStanislav Samsonov * EHCI2 187794d15b2SStanislav Samsonov ****************************************************************************/ 188794d15b2SStanislav Samsonov void __init mv78xx0_ehci2_init(void) 189794d15b2SStanislav Samsonov { 190db33f4deSAndrew Lunn orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); 191794d15b2SStanislav Samsonov } 192794d15b2SStanislav Samsonov 193794d15b2SStanislav Samsonov 194794d15b2SStanislav Samsonov /***************************************************************************** 195794d15b2SStanislav Samsonov * GE00 196794d15b2SStanislav Samsonov ****************************************************************************/ 197794d15b2SStanislav Samsonov void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 198794d15b2SStanislav Samsonov { 199db33f4deSAndrew Lunn orion_ge00_init(eth_data, 2007e3819d8SAndrew Lunn GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 2017e3819d8SAndrew Lunn IRQ_MV78XX0_GE_ERR, get_tclk()); 202794d15b2SStanislav Samsonov } 203794d15b2SStanislav Samsonov 204794d15b2SStanislav Samsonov 205794d15b2SStanislav Samsonov /***************************************************************************** 206794d15b2SStanislav Samsonov * GE01 207794d15b2SStanislav Samsonov ****************************************************************************/ 208794d15b2SStanislav Samsonov void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 209794d15b2SStanislav Samsonov { 210db33f4deSAndrew Lunn orion_ge01_init(eth_data, 2117e3819d8SAndrew Lunn GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 2127e3819d8SAndrew Lunn NO_IRQ, get_tclk()); 213794d15b2SStanislav Samsonov } 214794d15b2SStanislav Samsonov 215794d15b2SStanislav Samsonov 216794d15b2SStanislav Samsonov /***************************************************************************** 217794d15b2SStanislav Samsonov * GE10 218794d15b2SStanislav Samsonov ****************************************************************************/ 219794d15b2SStanislav Samsonov void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 220794d15b2SStanislav Samsonov { 221712424fdSLennert Buytenhek u32 dev, rev; 222712424fdSLennert Buytenhek 223712424fdSLennert Buytenhek /* 224712424fdSLennert Buytenhek * On the Z0, ge10 and ge11 are internally connected back 225712424fdSLennert Buytenhek * to back, and not brought out. 226712424fdSLennert Buytenhek */ 227712424fdSLennert Buytenhek mv78xx0_pcie_id(&dev, &rev); 228712424fdSLennert Buytenhek if (dev == MV78X00_Z0_DEV_ID) { 229712424fdSLennert Buytenhek eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 230712424fdSLennert Buytenhek eth_data->speed = SPEED_1000; 231712424fdSLennert Buytenhek eth_data->duplex = DUPLEX_FULL; 232712424fdSLennert Buytenhek } 233712424fdSLennert Buytenhek 234db33f4deSAndrew Lunn orion_ge10_init(eth_data, 2357e3819d8SAndrew Lunn GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 2367e3819d8SAndrew Lunn NO_IRQ, get_tclk()); 237794d15b2SStanislav Samsonov } 238794d15b2SStanislav Samsonov 239794d15b2SStanislav Samsonov 240794d15b2SStanislav Samsonov /***************************************************************************** 241794d15b2SStanislav Samsonov * GE11 242794d15b2SStanislav Samsonov ****************************************************************************/ 243794d15b2SStanislav Samsonov void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 244794d15b2SStanislav Samsonov { 245712424fdSLennert Buytenhek u32 dev, rev; 246712424fdSLennert Buytenhek 247712424fdSLennert Buytenhek /* 248712424fdSLennert Buytenhek * On the Z0, ge10 and ge11 are internally connected back 249712424fdSLennert Buytenhek * to back, and not brought out. 250712424fdSLennert Buytenhek */ 251712424fdSLennert Buytenhek mv78xx0_pcie_id(&dev, &rev); 252712424fdSLennert Buytenhek if (dev == MV78X00_Z0_DEV_ID) { 253712424fdSLennert Buytenhek eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 254712424fdSLennert Buytenhek eth_data->speed = SPEED_1000; 255712424fdSLennert Buytenhek eth_data->duplex = DUPLEX_FULL; 256712424fdSLennert Buytenhek } 257712424fdSLennert Buytenhek 258db33f4deSAndrew Lunn orion_ge11_init(eth_data, 2597e3819d8SAndrew Lunn GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 2607e3819d8SAndrew Lunn NO_IRQ, get_tclk()); 261794d15b2SStanislav Samsonov } 262794d15b2SStanislav Samsonov 26369359943SRiku Voipio /***************************************************************************** 264aac7ffa3SAndrew Lunn * I2C 26569359943SRiku Voipio ****************************************************************************/ 26669359943SRiku Voipio void __init mv78xx0_i2c_init(void) 26769359943SRiku Voipio { 268aac7ffa3SAndrew Lunn orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); 269aac7ffa3SAndrew Lunn orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); 27069359943SRiku Voipio } 271794d15b2SStanislav Samsonov 272794d15b2SStanislav Samsonov /***************************************************************************** 273794d15b2SStanislav Samsonov * SATA 274794d15b2SStanislav Samsonov ****************************************************************************/ 275794d15b2SStanislav Samsonov void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 276794d15b2SStanislav Samsonov { 277db33f4deSAndrew Lunn orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); 278794d15b2SStanislav Samsonov } 279794d15b2SStanislav Samsonov 280794d15b2SStanislav Samsonov 281794d15b2SStanislav Samsonov /***************************************************************************** 282794d15b2SStanislav Samsonov * UART0 283794d15b2SStanislav Samsonov ****************************************************************************/ 284794d15b2SStanislav Samsonov void __init mv78xx0_uart0_init(void) 285794d15b2SStanislav Samsonov { 28628a2b450SAndrew Lunn orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 28728a2b450SAndrew Lunn IRQ_MV78XX0_UART_0, get_tclk()); 288794d15b2SStanislav Samsonov } 289794d15b2SStanislav Samsonov 290794d15b2SStanislav Samsonov 291794d15b2SStanislav Samsonov /***************************************************************************** 292794d15b2SStanislav Samsonov * UART1 293794d15b2SStanislav Samsonov ****************************************************************************/ 294794d15b2SStanislav Samsonov void __init mv78xx0_uart1_init(void) 295794d15b2SStanislav Samsonov { 29628a2b450SAndrew Lunn orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 29728a2b450SAndrew Lunn IRQ_MV78XX0_UART_1, get_tclk()); 298794d15b2SStanislav Samsonov } 299794d15b2SStanislav Samsonov 300794d15b2SStanislav Samsonov 301794d15b2SStanislav Samsonov /***************************************************************************** 302794d15b2SStanislav Samsonov * UART2 303794d15b2SStanislav Samsonov ****************************************************************************/ 304794d15b2SStanislav Samsonov void __init mv78xx0_uart2_init(void) 305794d15b2SStanislav Samsonov { 30628a2b450SAndrew Lunn orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, 30728a2b450SAndrew Lunn IRQ_MV78XX0_UART_2, get_tclk()); 308794d15b2SStanislav Samsonov } 309794d15b2SStanislav Samsonov 310794d15b2SStanislav Samsonov /***************************************************************************** 311794d15b2SStanislav Samsonov * UART3 312794d15b2SStanislav Samsonov ****************************************************************************/ 313794d15b2SStanislav Samsonov void __init mv78xx0_uart3_init(void) 314794d15b2SStanislav Samsonov { 31528a2b450SAndrew Lunn orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, 31628a2b450SAndrew Lunn IRQ_MV78XX0_UART_3, get_tclk()); 317794d15b2SStanislav Samsonov } 318794d15b2SStanislav Samsonov 319794d15b2SStanislav Samsonov /***************************************************************************** 320794d15b2SStanislav Samsonov * Time handling 321794d15b2SStanislav Samsonov ****************************************************************************/ 3224ee1f6b5SLennert Buytenhek void __init mv78xx0_init_early(void) 3234ee1f6b5SLennert Buytenhek { 3244ee1f6b5SLennert Buytenhek orion_time_set_base(TIMER_VIRT_BASE); 3254ee1f6b5SLennert Buytenhek } 3264ee1f6b5SLennert Buytenhek 327794d15b2SStanislav Samsonov static void mv78xx0_timer_init(void) 328794d15b2SStanislav Samsonov { 3294ee1f6b5SLennert Buytenhek orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 3304ee1f6b5SLennert Buytenhek IRQ_MV78XX0_TIMER_1, get_tclk()); 331794d15b2SStanislav Samsonov } 332794d15b2SStanislav Samsonov 333794d15b2SStanislav Samsonov struct sys_timer mv78xx0_timer = { 334794d15b2SStanislav Samsonov .init = mv78xx0_timer_init, 335794d15b2SStanislav Samsonov }; 336794d15b2SStanislav Samsonov 337794d15b2SStanislav Samsonov 338794d15b2SStanislav Samsonov /***************************************************************************** 339794d15b2SStanislav Samsonov * General 340794d15b2SStanislav Samsonov ****************************************************************************/ 341cfdeb637SLennert Buytenhek static char * __init mv78xx0_id(void) 342cfdeb637SLennert Buytenhek { 343cfdeb637SLennert Buytenhek u32 dev, rev; 344cfdeb637SLennert Buytenhek 345cfdeb637SLennert Buytenhek mv78xx0_pcie_id(&dev, &rev); 346cfdeb637SLennert Buytenhek 347cfdeb637SLennert Buytenhek if (dev == MV78X00_Z0_DEV_ID) { 348cfdeb637SLennert Buytenhek if (rev == MV78X00_REV_Z0) 349cfdeb637SLennert Buytenhek return "MV78X00-Z0"; 350cfdeb637SLennert Buytenhek else 351cfdeb637SLennert Buytenhek return "MV78X00-Rev-Unsupported"; 352cfdeb637SLennert Buytenhek } else if (dev == MV78100_DEV_ID) { 353cfdeb637SLennert Buytenhek if (rev == MV78100_REV_A0) 354cfdeb637SLennert Buytenhek return "MV78100-A0"; 355662aecedSLennert Buytenhek else if (rev == MV78100_REV_A1) 356662aecedSLennert Buytenhek return "MV78100-A1"; 357cfdeb637SLennert Buytenhek else 358cfdeb637SLennert Buytenhek return "MV78100-Rev-Unsupported"; 359cfdeb637SLennert Buytenhek } else if (dev == MV78200_DEV_ID) { 360cfdeb637SLennert Buytenhek if (rev == MV78100_REV_A0) 361cfdeb637SLennert Buytenhek return "MV78200-A0"; 362cfdeb637SLennert Buytenhek else 363cfdeb637SLennert Buytenhek return "MV78200-Rev-Unsupported"; 364cfdeb637SLennert Buytenhek } else { 365cfdeb637SLennert Buytenhek return "Device-Unknown"; 366cfdeb637SLennert Buytenhek } 367cfdeb637SLennert Buytenhek } 368cfdeb637SLennert Buytenhek 369794d15b2SStanislav Samsonov static int __init is_l2_writethrough(void) 370794d15b2SStanislav Samsonov { 371794d15b2SStanislav Samsonov return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); 372794d15b2SStanislav Samsonov } 373794d15b2SStanislav Samsonov 374794d15b2SStanislav Samsonov void __init mv78xx0_init(void) 375794d15b2SStanislav Samsonov { 376794d15b2SStanislav Samsonov int core_index; 377794d15b2SStanislav Samsonov int hclk; 378794d15b2SStanislav Samsonov int pclk; 379794d15b2SStanislav Samsonov int l2clk; 380794d15b2SStanislav Samsonov int tclk; 381794d15b2SStanislav Samsonov 382794d15b2SStanislav Samsonov core_index = mv78xx0_core_index(); 383794d15b2SStanislav Samsonov hclk = get_hclk(); 384794d15b2SStanislav Samsonov get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); 385794d15b2SStanislav Samsonov tclk = get_tclk(); 386794d15b2SStanislav Samsonov 387cfdeb637SLennert Buytenhek printk(KERN_INFO "%s ", mv78xx0_id()); 388cfdeb637SLennert Buytenhek printk("core #%d, ", core_index); 389794d15b2SStanislav Samsonov printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); 390794d15b2SStanislav Samsonov printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); 391794d15b2SStanislav Samsonov printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 392794d15b2SStanislav Samsonov printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); 393794d15b2SStanislav Samsonov 394794d15b2SStanislav Samsonov mv78xx0_setup_cpu_mbus(); 395794d15b2SStanislav Samsonov 396794d15b2SStanislav Samsonov #ifdef CONFIG_CACHE_FEROCEON_L2 397794d15b2SStanislav Samsonov feroceon_l2_init(is_l2_writethrough()); 398794d15b2SStanislav Samsonov #endif 399794d15b2SStanislav Samsonov } 400