1794d15b2SStanislav Samsonov /* 2794d15b2SStanislav Samsonov * arch/arm/mach-mv78xx0/common.c 3794d15b2SStanislav Samsonov * 4794d15b2SStanislav Samsonov * Core functions for Marvell MV78xx0 SoCs 5794d15b2SStanislav Samsonov * 6794d15b2SStanislav Samsonov * This file is licensed under the terms of the GNU General Public 7794d15b2SStanislav Samsonov * License version 2. This program is licensed "as is" without any 8794d15b2SStanislav Samsonov * warranty of any kind, whether express or implied. 9794d15b2SStanislav Samsonov */ 10794d15b2SStanislav Samsonov 11794d15b2SStanislav Samsonov #include <linux/kernel.h> 12794d15b2SStanislav Samsonov #include <linux/init.h> 13794d15b2SStanislav Samsonov #include <linux/platform_device.h> 14794d15b2SStanislav Samsonov #include <linux/serial_8250.h> 15794d15b2SStanislav Samsonov #include <linux/mbus.h> 16794d15b2SStanislav Samsonov #include <linux/ata_platform.h> 17712424fdSLennert Buytenhek #include <linux/ethtool.h> 18794d15b2SStanislav Samsonov #include <asm/mach/map.h> 19794d15b2SStanislav Samsonov #include <asm/mach/time.h> 20a09e64fbSRussell King #include <mach/mv78xx0.h> 21fdd8b079SNicolas Pitre #include <mach/bridge-regs.h> 226f088f1dSLennert Buytenhek #include <plat/cache-feroceon-l2.h> 236f088f1dSLennert Buytenhek #include <plat/ehci-orion.h> 246f088f1dSLennert Buytenhek #include <plat/orion_nand.h> 256f088f1dSLennert Buytenhek #include <plat/time.h> 2628a2b450SAndrew Lunn #include <plat/common.h> 27794d15b2SStanislav Samsonov #include "common.h" 28794d15b2SStanislav Samsonov 2928a2b450SAndrew Lunn static int get_tclk(void); 30794d15b2SStanislav Samsonov 31794d15b2SStanislav Samsonov /***************************************************************************** 32794d15b2SStanislav Samsonov * Common bits 33794d15b2SStanislav Samsonov ****************************************************************************/ 34794d15b2SStanislav Samsonov int mv78xx0_core_index(void) 35794d15b2SStanislav Samsonov { 36794d15b2SStanislav Samsonov u32 extra; 37794d15b2SStanislav Samsonov 38794d15b2SStanislav Samsonov /* 39794d15b2SStanislav Samsonov * Read Extra Features register. 40794d15b2SStanislav Samsonov */ 41794d15b2SStanislav Samsonov __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); 42794d15b2SStanislav Samsonov 43794d15b2SStanislav Samsonov return !!(extra & 0x00004000); 44794d15b2SStanislav Samsonov } 45794d15b2SStanislav Samsonov 46794d15b2SStanislav Samsonov static int get_hclk(void) 47794d15b2SStanislav Samsonov { 48794d15b2SStanislav Samsonov int hclk; 49794d15b2SStanislav Samsonov 50794d15b2SStanislav Samsonov /* 51794d15b2SStanislav Samsonov * HCLK tick rate is configured by DEV_D[7:5] pins. 52794d15b2SStanislav Samsonov */ 53794d15b2SStanislav Samsonov switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { 54794d15b2SStanislav Samsonov case 0: 55794d15b2SStanislav Samsonov hclk = 166666667; 56794d15b2SStanislav Samsonov break; 57794d15b2SStanislav Samsonov case 1: 58794d15b2SStanislav Samsonov hclk = 200000000; 59794d15b2SStanislav Samsonov break; 60794d15b2SStanislav Samsonov case 2: 61794d15b2SStanislav Samsonov hclk = 266666667; 62794d15b2SStanislav Samsonov break; 63794d15b2SStanislav Samsonov case 3: 64794d15b2SStanislav Samsonov hclk = 333333333; 65794d15b2SStanislav Samsonov break; 66794d15b2SStanislav Samsonov case 4: 67794d15b2SStanislav Samsonov hclk = 400000000; 68794d15b2SStanislav Samsonov break; 69794d15b2SStanislav Samsonov default: 70794d15b2SStanislav Samsonov panic("unknown HCLK PLL setting: %.8x\n", 71794d15b2SStanislav Samsonov readl(SAMPLE_AT_RESET_LOW)); 72794d15b2SStanislav Samsonov } 73794d15b2SStanislav Samsonov 74794d15b2SStanislav Samsonov return hclk; 75794d15b2SStanislav Samsonov } 76794d15b2SStanislav Samsonov 77794d15b2SStanislav Samsonov static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) 78794d15b2SStanislav Samsonov { 79794d15b2SStanislav Samsonov u32 cfg; 80794d15b2SStanislav Samsonov 81794d15b2SStanislav Samsonov /* 82794d15b2SStanislav Samsonov * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 83794d15b2SStanislav Samsonov * PCLK/L2CLK by bits [19:14]. 84794d15b2SStanislav Samsonov */ 85794d15b2SStanislav Samsonov if (core_index == 0) { 86794d15b2SStanislav Samsonov cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; 87794d15b2SStanislav Samsonov } else { 88794d15b2SStanislav Samsonov cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; 89794d15b2SStanislav Samsonov } 90794d15b2SStanislav Samsonov 91794d15b2SStanislav Samsonov /* 92794d15b2SStanislav Samsonov * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK 93794d15b2SStanislav Samsonov * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). 94794d15b2SStanislav Samsonov */ 95794d15b2SStanislav Samsonov *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; 96794d15b2SStanislav Samsonov 97794d15b2SStanislav Samsonov /* 98794d15b2SStanislav Samsonov * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK 99794d15b2SStanislav Samsonov * ratio (1, 2, 3). 100794d15b2SStanislav Samsonov */ 101794d15b2SStanislav Samsonov *l2clk = *pclk / (((cfg >> 4) & 3) + 1); 102794d15b2SStanislav Samsonov } 103794d15b2SStanislav Samsonov 104794d15b2SStanislav Samsonov static int get_tclk(void) 105794d15b2SStanislav Samsonov { 106794d15b2SStanislav Samsonov int tclk; 107794d15b2SStanislav Samsonov 108794d15b2SStanislav Samsonov /* 109794d15b2SStanislav Samsonov * TCLK tick rate is configured by DEV_A[2:0] strap pins. 110794d15b2SStanislav Samsonov */ 111794d15b2SStanislav Samsonov switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { 112794d15b2SStanislav Samsonov case 1: 113794d15b2SStanislav Samsonov tclk = 166666667; 114794d15b2SStanislav Samsonov break; 115794d15b2SStanislav Samsonov case 3: 116794d15b2SStanislav Samsonov tclk = 200000000; 117794d15b2SStanislav Samsonov break; 118794d15b2SStanislav Samsonov default: 119794d15b2SStanislav Samsonov panic("unknown TCLK PLL setting: %.8x\n", 120794d15b2SStanislav Samsonov readl(SAMPLE_AT_RESET_HIGH)); 121794d15b2SStanislav Samsonov } 122794d15b2SStanislav Samsonov 123794d15b2SStanislav Samsonov return tclk; 124794d15b2SStanislav Samsonov } 125794d15b2SStanislav Samsonov 126794d15b2SStanislav Samsonov 127794d15b2SStanislav Samsonov /***************************************************************************** 128794d15b2SStanislav Samsonov * I/O Address Mapping 129794d15b2SStanislav Samsonov ****************************************************************************/ 130794d15b2SStanislav Samsonov static struct map_desc mv78xx0_io_desc[] __initdata = { 131794d15b2SStanislav Samsonov { 132794d15b2SStanislav Samsonov .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 133794d15b2SStanislav Samsonov .pfn = 0, 134794d15b2SStanislav Samsonov .length = MV78XX0_CORE_REGS_SIZE, 135794d15b2SStanislav Samsonov .type = MT_DEVICE, 136794d15b2SStanislav Samsonov }, { 137794d15b2SStanislav Samsonov .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), 138794d15b2SStanislav Samsonov .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), 139794d15b2SStanislav Samsonov .length = MV78XX0_PCIE_IO_SIZE * 8, 140794d15b2SStanislav Samsonov .type = MT_DEVICE, 141794d15b2SStanislav Samsonov }, { 142794d15b2SStanislav Samsonov .virtual = MV78XX0_REGS_VIRT_BASE, 143794d15b2SStanislav Samsonov .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 144794d15b2SStanislav Samsonov .length = MV78XX0_REGS_SIZE, 145794d15b2SStanislav Samsonov .type = MT_DEVICE, 146794d15b2SStanislav Samsonov }, 147794d15b2SStanislav Samsonov }; 148794d15b2SStanislav Samsonov 149794d15b2SStanislav Samsonov void __init mv78xx0_map_io(void) 150794d15b2SStanislav Samsonov { 151794d15b2SStanislav Samsonov unsigned long phys; 152794d15b2SStanislav Samsonov 153794d15b2SStanislav Samsonov /* 154794d15b2SStanislav Samsonov * Map the right set of per-core registers depending on 155794d15b2SStanislav Samsonov * which core we are running on. 156794d15b2SStanislav Samsonov */ 157794d15b2SStanislav Samsonov if (mv78xx0_core_index() == 0) { 158794d15b2SStanislav Samsonov phys = MV78XX0_CORE0_REGS_PHYS_BASE; 159794d15b2SStanislav Samsonov } else { 160794d15b2SStanislav Samsonov phys = MV78XX0_CORE1_REGS_PHYS_BASE; 161794d15b2SStanislav Samsonov } 162794d15b2SStanislav Samsonov mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); 163794d15b2SStanislav Samsonov 164794d15b2SStanislav Samsonov iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); 165794d15b2SStanislav Samsonov } 166794d15b2SStanislav Samsonov 167794d15b2SStanislav Samsonov 168794d15b2SStanislav Samsonov /***************************************************************************** 169794d15b2SStanislav Samsonov * EHCI 170794d15b2SStanislav Samsonov ****************************************************************************/ 171794d15b2SStanislav Samsonov static struct orion_ehci_data mv78xx0_ehci_data = { 172794d15b2SStanislav Samsonov .dram = &mv78xx0_mbus_dram_info, 173fb6f5529SRonen Shitrit .phy_version = EHCI_PHY_NA, 174794d15b2SStanislav Samsonov }; 175794d15b2SStanislav Samsonov 1765c602551SAndrew Lunn static u64 ehci_dmamask = DMA_BIT_MASK(32); 177794d15b2SStanislav Samsonov 178794d15b2SStanislav Samsonov 179794d15b2SStanislav Samsonov /***************************************************************************** 180794d15b2SStanislav Samsonov * EHCI0 181794d15b2SStanislav Samsonov ****************************************************************************/ 182794d15b2SStanislav Samsonov static struct resource mv78xx0_ehci0_resources[] = { 183794d15b2SStanislav Samsonov { 184794d15b2SStanislav Samsonov .start = USB0_PHYS_BASE, 1855c602551SAndrew Lunn .end = USB0_PHYS_BASE + SZ_4K - 1, 186794d15b2SStanislav Samsonov .flags = IORESOURCE_MEM, 187794d15b2SStanislav Samsonov }, { 188794d15b2SStanislav Samsonov .start = IRQ_MV78XX0_USB_0, 189794d15b2SStanislav Samsonov .end = IRQ_MV78XX0_USB_0, 190794d15b2SStanislav Samsonov .flags = IORESOURCE_IRQ, 191794d15b2SStanislav Samsonov }, 192794d15b2SStanislav Samsonov }; 193794d15b2SStanislav Samsonov 194794d15b2SStanislav Samsonov static struct platform_device mv78xx0_ehci0 = { 195794d15b2SStanislav Samsonov .name = "orion-ehci", 196794d15b2SStanislav Samsonov .id = 0, 197794d15b2SStanislav Samsonov .dev = { 198794d15b2SStanislav Samsonov .dma_mask = &ehci_dmamask, 1995c602551SAndrew Lunn .coherent_dma_mask = DMA_BIT_MASK(32), 200794d15b2SStanislav Samsonov .platform_data = &mv78xx0_ehci_data, 201794d15b2SStanislav Samsonov }, 202794d15b2SStanislav Samsonov .resource = mv78xx0_ehci0_resources, 203794d15b2SStanislav Samsonov .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), 204794d15b2SStanislav Samsonov }; 205794d15b2SStanislav Samsonov 206794d15b2SStanislav Samsonov void __init mv78xx0_ehci0_init(void) 207794d15b2SStanislav Samsonov { 208794d15b2SStanislav Samsonov platform_device_register(&mv78xx0_ehci0); 209794d15b2SStanislav Samsonov } 210794d15b2SStanislav Samsonov 211794d15b2SStanislav Samsonov 212794d15b2SStanislav Samsonov /***************************************************************************** 213794d15b2SStanislav Samsonov * EHCI1 214794d15b2SStanislav Samsonov ****************************************************************************/ 215794d15b2SStanislav Samsonov static struct resource mv78xx0_ehci1_resources[] = { 216794d15b2SStanislav Samsonov { 217794d15b2SStanislav Samsonov .start = USB1_PHYS_BASE, 2185c602551SAndrew Lunn .end = USB1_PHYS_BASE + SZ_4K - 1, 219794d15b2SStanislav Samsonov .flags = IORESOURCE_MEM, 220794d15b2SStanislav Samsonov }, { 221794d15b2SStanislav Samsonov .start = IRQ_MV78XX0_USB_1, 222794d15b2SStanislav Samsonov .end = IRQ_MV78XX0_USB_1, 223794d15b2SStanislav Samsonov .flags = IORESOURCE_IRQ, 224794d15b2SStanislav Samsonov }, 225794d15b2SStanislav Samsonov }; 226794d15b2SStanislav Samsonov 227794d15b2SStanislav Samsonov static struct platform_device mv78xx0_ehci1 = { 228794d15b2SStanislav Samsonov .name = "orion-ehci", 229794d15b2SStanislav Samsonov .id = 1, 230794d15b2SStanislav Samsonov .dev = { 231794d15b2SStanislav Samsonov .dma_mask = &ehci_dmamask, 2325c602551SAndrew Lunn .coherent_dma_mask = DMA_BIT_MASK(32), 233794d15b2SStanislav Samsonov .platform_data = &mv78xx0_ehci_data, 234794d15b2SStanislav Samsonov }, 235794d15b2SStanislav Samsonov .resource = mv78xx0_ehci1_resources, 236794d15b2SStanislav Samsonov .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), 237794d15b2SStanislav Samsonov }; 238794d15b2SStanislav Samsonov 239794d15b2SStanislav Samsonov void __init mv78xx0_ehci1_init(void) 240794d15b2SStanislav Samsonov { 241794d15b2SStanislav Samsonov platform_device_register(&mv78xx0_ehci1); 242794d15b2SStanislav Samsonov } 243794d15b2SStanislav Samsonov 244794d15b2SStanislav Samsonov 245794d15b2SStanislav Samsonov /***************************************************************************** 246794d15b2SStanislav Samsonov * EHCI2 247794d15b2SStanislav Samsonov ****************************************************************************/ 248794d15b2SStanislav Samsonov static struct resource mv78xx0_ehci2_resources[] = { 249794d15b2SStanislav Samsonov { 250794d15b2SStanislav Samsonov .start = USB2_PHYS_BASE, 2515c602551SAndrew Lunn .end = USB2_PHYS_BASE + SZ_4K - 1, 252794d15b2SStanislav Samsonov .flags = IORESOURCE_MEM, 253794d15b2SStanislav Samsonov }, { 254794d15b2SStanislav Samsonov .start = IRQ_MV78XX0_USB_2, 255794d15b2SStanislav Samsonov .end = IRQ_MV78XX0_USB_2, 256794d15b2SStanislav Samsonov .flags = IORESOURCE_IRQ, 257794d15b2SStanislav Samsonov }, 258794d15b2SStanislav Samsonov }; 259794d15b2SStanislav Samsonov 260794d15b2SStanislav Samsonov static struct platform_device mv78xx0_ehci2 = { 261794d15b2SStanislav Samsonov .name = "orion-ehci", 262794d15b2SStanislav Samsonov .id = 2, 263794d15b2SStanislav Samsonov .dev = { 264794d15b2SStanislav Samsonov .dma_mask = &ehci_dmamask, 2655c602551SAndrew Lunn .coherent_dma_mask = DMA_BIT_MASK(32), 266794d15b2SStanislav Samsonov .platform_data = &mv78xx0_ehci_data, 267794d15b2SStanislav Samsonov }, 268794d15b2SStanislav Samsonov .resource = mv78xx0_ehci2_resources, 269794d15b2SStanislav Samsonov .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), 270794d15b2SStanislav Samsonov }; 271794d15b2SStanislav Samsonov 272794d15b2SStanislav Samsonov void __init mv78xx0_ehci2_init(void) 273794d15b2SStanislav Samsonov { 274794d15b2SStanislav Samsonov platform_device_register(&mv78xx0_ehci2); 275794d15b2SStanislav Samsonov } 276794d15b2SStanislav Samsonov 277794d15b2SStanislav Samsonov 278794d15b2SStanislav Samsonov /***************************************************************************** 279794d15b2SStanislav Samsonov * GE00 280794d15b2SStanislav Samsonov ****************************************************************************/ 281794d15b2SStanislav Samsonov void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 282794d15b2SStanislav Samsonov { 2837e3819d8SAndrew Lunn orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, 2847e3819d8SAndrew Lunn GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 2857e3819d8SAndrew Lunn IRQ_MV78XX0_GE_ERR, get_tclk()); 286794d15b2SStanislav Samsonov } 287794d15b2SStanislav Samsonov 288794d15b2SStanislav Samsonov 289794d15b2SStanislav Samsonov /***************************************************************************** 290794d15b2SStanislav Samsonov * GE01 291794d15b2SStanislav Samsonov ****************************************************************************/ 292794d15b2SStanislav Samsonov void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 293794d15b2SStanislav Samsonov { 2947e3819d8SAndrew Lunn orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, 2957e3819d8SAndrew Lunn GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 2967e3819d8SAndrew Lunn NO_IRQ, get_tclk()); 297794d15b2SStanislav Samsonov } 298794d15b2SStanislav Samsonov 299794d15b2SStanislav Samsonov 300794d15b2SStanislav Samsonov /***************************************************************************** 301794d15b2SStanislav Samsonov * GE10 302794d15b2SStanislav Samsonov ****************************************************************************/ 303794d15b2SStanislav Samsonov void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 304794d15b2SStanislav Samsonov { 305712424fdSLennert Buytenhek u32 dev, rev; 306712424fdSLennert Buytenhek 307712424fdSLennert Buytenhek /* 308712424fdSLennert Buytenhek * On the Z0, ge10 and ge11 are internally connected back 309712424fdSLennert Buytenhek * to back, and not brought out. 310712424fdSLennert Buytenhek */ 311712424fdSLennert Buytenhek mv78xx0_pcie_id(&dev, &rev); 312712424fdSLennert Buytenhek if (dev == MV78X00_Z0_DEV_ID) { 313712424fdSLennert Buytenhek eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 314712424fdSLennert Buytenhek eth_data->speed = SPEED_1000; 315712424fdSLennert Buytenhek eth_data->duplex = DUPLEX_FULL; 316712424fdSLennert Buytenhek } 317712424fdSLennert Buytenhek 3187e3819d8SAndrew Lunn orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, 3197e3819d8SAndrew Lunn GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 3207e3819d8SAndrew Lunn NO_IRQ, get_tclk()); 321794d15b2SStanislav Samsonov } 322794d15b2SStanislav Samsonov 323794d15b2SStanislav Samsonov 324794d15b2SStanislav Samsonov /***************************************************************************** 325794d15b2SStanislav Samsonov * GE11 326794d15b2SStanislav Samsonov ****************************************************************************/ 327794d15b2SStanislav Samsonov void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 328794d15b2SStanislav Samsonov { 329712424fdSLennert Buytenhek u32 dev, rev; 330712424fdSLennert Buytenhek 331712424fdSLennert Buytenhek /* 332712424fdSLennert Buytenhek * On the Z0, ge10 and ge11 are internally connected back 333712424fdSLennert Buytenhek * to back, and not brought out. 334712424fdSLennert Buytenhek */ 335712424fdSLennert Buytenhek mv78xx0_pcie_id(&dev, &rev); 336712424fdSLennert Buytenhek if (dev == MV78X00_Z0_DEV_ID) { 337712424fdSLennert Buytenhek eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 338712424fdSLennert Buytenhek eth_data->speed = SPEED_1000; 339712424fdSLennert Buytenhek eth_data->duplex = DUPLEX_FULL; 340712424fdSLennert Buytenhek } 341712424fdSLennert Buytenhek 3427e3819d8SAndrew Lunn orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, 3437e3819d8SAndrew Lunn GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 3447e3819d8SAndrew Lunn NO_IRQ, get_tclk()); 345794d15b2SStanislav Samsonov } 346794d15b2SStanislav Samsonov 34769359943SRiku Voipio /***************************************************************************** 348aac7ffa3SAndrew Lunn * I2C 34969359943SRiku Voipio ****************************************************************************/ 35069359943SRiku Voipio void __init mv78xx0_i2c_init(void) 35169359943SRiku Voipio { 352aac7ffa3SAndrew Lunn orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); 353aac7ffa3SAndrew Lunn orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); 35469359943SRiku Voipio } 355794d15b2SStanislav Samsonov 356794d15b2SStanislav Samsonov /***************************************************************************** 357794d15b2SStanislav Samsonov * SATA 358794d15b2SStanislav Samsonov ****************************************************************************/ 359794d15b2SStanislav Samsonov static struct resource mv78xx0_sata_resources[] = { 360794d15b2SStanislav Samsonov { 361794d15b2SStanislav Samsonov .name = "sata base", 362794d15b2SStanislav Samsonov .start = SATA_PHYS_BASE, 363794d15b2SStanislav Samsonov .end = SATA_PHYS_BASE + 0x5000 - 1, 364794d15b2SStanislav Samsonov .flags = IORESOURCE_MEM, 365794d15b2SStanislav Samsonov }, { 366794d15b2SStanislav Samsonov .name = "sata irq", 367794d15b2SStanislav Samsonov .start = IRQ_MV78XX0_SATA, 368794d15b2SStanislav Samsonov .end = IRQ_MV78XX0_SATA, 369794d15b2SStanislav Samsonov .flags = IORESOURCE_IRQ, 370794d15b2SStanislav Samsonov }, 371794d15b2SStanislav Samsonov }; 372794d15b2SStanislav Samsonov 373794d15b2SStanislav Samsonov static struct platform_device mv78xx0_sata = { 374794d15b2SStanislav Samsonov .name = "sata_mv", 375794d15b2SStanislav Samsonov .id = 0, 376794d15b2SStanislav Samsonov .dev = { 3775c602551SAndrew Lunn .coherent_dma_mask = DMA_BIT_MASK(32), 378794d15b2SStanislav Samsonov }, 379794d15b2SStanislav Samsonov .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), 380794d15b2SStanislav Samsonov .resource = mv78xx0_sata_resources, 381794d15b2SStanislav Samsonov }; 382794d15b2SStanislav Samsonov 383794d15b2SStanislav Samsonov void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 384794d15b2SStanislav Samsonov { 385794d15b2SStanislav Samsonov sata_data->dram = &mv78xx0_mbus_dram_info; 386794d15b2SStanislav Samsonov mv78xx0_sata.dev.platform_data = sata_data; 387794d15b2SStanislav Samsonov platform_device_register(&mv78xx0_sata); 388794d15b2SStanislav Samsonov } 389794d15b2SStanislav Samsonov 390794d15b2SStanislav Samsonov 391794d15b2SStanislav Samsonov /***************************************************************************** 392794d15b2SStanislav Samsonov * UART0 393794d15b2SStanislav Samsonov ****************************************************************************/ 394794d15b2SStanislav Samsonov void __init mv78xx0_uart0_init(void) 395794d15b2SStanislav Samsonov { 39628a2b450SAndrew Lunn orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 39728a2b450SAndrew Lunn IRQ_MV78XX0_UART_0, get_tclk()); 398794d15b2SStanislav Samsonov } 399794d15b2SStanislav Samsonov 400794d15b2SStanislav Samsonov 401794d15b2SStanislav Samsonov /***************************************************************************** 402794d15b2SStanislav Samsonov * UART1 403794d15b2SStanislav Samsonov ****************************************************************************/ 404794d15b2SStanislav Samsonov void __init mv78xx0_uart1_init(void) 405794d15b2SStanislav Samsonov { 40628a2b450SAndrew Lunn orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 40728a2b450SAndrew Lunn IRQ_MV78XX0_UART_1, get_tclk()); 408794d15b2SStanislav Samsonov } 409794d15b2SStanislav Samsonov 410794d15b2SStanislav Samsonov 411794d15b2SStanislav Samsonov /***************************************************************************** 412794d15b2SStanislav Samsonov * UART2 413794d15b2SStanislav Samsonov ****************************************************************************/ 414794d15b2SStanislav Samsonov void __init mv78xx0_uart2_init(void) 415794d15b2SStanislav Samsonov { 41628a2b450SAndrew Lunn orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, 41728a2b450SAndrew Lunn IRQ_MV78XX0_UART_2, get_tclk()); 418794d15b2SStanislav Samsonov } 419794d15b2SStanislav Samsonov 420794d15b2SStanislav Samsonov /***************************************************************************** 421794d15b2SStanislav Samsonov * UART3 422794d15b2SStanislav Samsonov ****************************************************************************/ 423794d15b2SStanislav Samsonov void __init mv78xx0_uart3_init(void) 424794d15b2SStanislav Samsonov { 42528a2b450SAndrew Lunn orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, 42628a2b450SAndrew Lunn IRQ_MV78XX0_UART_3, get_tclk()); 427794d15b2SStanislav Samsonov } 428794d15b2SStanislav Samsonov 429794d15b2SStanislav Samsonov /***************************************************************************** 430794d15b2SStanislav Samsonov * Time handling 431794d15b2SStanislav Samsonov ****************************************************************************/ 4324ee1f6b5SLennert Buytenhek void __init mv78xx0_init_early(void) 4334ee1f6b5SLennert Buytenhek { 4344ee1f6b5SLennert Buytenhek orion_time_set_base(TIMER_VIRT_BASE); 4354ee1f6b5SLennert Buytenhek } 4364ee1f6b5SLennert Buytenhek 437794d15b2SStanislav Samsonov static void mv78xx0_timer_init(void) 438794d15b2SStanislav Samsonov { 4394ee1f6b5SLennert Buytenhek orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 4404ee1f6b5SLennert Buytenhek IRQ_MV78XX0_TIMER_1, get_tclk()); 441794d15b2SStanislav Samsonov } 442794d15b2SStanislav Samsonov 443794d15b2SStanislav Samsonov struct sys_timer mv78xx0_timer = { 444794d15b2SStanislav Samsonov .init = mv78xx0_timer_init, 445794d15b2SStanislav Samsonov }; 446794d15b2SStanislav Samsonov 447794d15b2SStanislav Samsonov 448794d15b2SStanislav Samsonov /***************************************************************************** 449794d15b2SStanislav Samsonov * General 450794d15b2SStanislav Samsonov ****************************************************************************/ 451cfdeb637SLennert Buytenhek static char * __init mv78xx0_id(void) 452cfdeb637SLennert Buytenhek { 453cfdeb637SLennert Buytenhek u32 dev, rev; 454cfdeb637SLennert Buytenhek 455cfdeb637SLennert Buytenhek mv78xx0_pcie_id(&dev, &rev); 456cfdeb637SLennert Buytenhek 457cfdeb637SLennert Buytenhek if (dev == MV78X00_Z0_DEV_ID) { 458cfdeb637SLennert Buytenhek if (rev == MV78X00_REV_Z0) 459cfdeb637SLennert Buytenhek return "MV78X00-Z0"; 460cfdeb637SLennert Buytenhek else 461cfdeb637SLennert Buytenhek return "MV78X00-Rev-Unsupported"; 462cfdeb637SLennert Buytenhek } else if (dev == MV78100_DEV_ID) { 463cfdeb637SLennert Buytenhek if (rev == MV78100_REV_A0) 464cfdeb637SLennert Buytenhek return "MV78100-A0"; 465662aecedSLennert Buytenhek else if (rev == MV78100_REV_A1) 466662aecedSLennert Buytenhek return "MV78100-A1"; 467cfdeb637SLennert Buytenhek else 468cfdeb637SLennert Buytenhek return "MV78100-Rev-Unsupported"; 469cfdeb637SLennert Buytenhek } else if (dev == MV78200_DEV_ID) { 470cfdeb637SLennert Buytenhek if (rev == MV78100_REV_A0) 471cfdeb637SLennert Buytenhek return "MV78200-A0"; 472cfdeb637SLennert Buytenhek else 473cfdeb637SLennert Buytenhek return "MV78200-Rev-Unsupported"; 474cfdeb637SLennert Buytenhek } else { 475cfdeb637SLennert Buytenhek return "Device-Unknown"; 476cfdeb637SLennert Buytenhek } 477cfdeb637SLennert Buytenhek } 478cfdeb637SLennert Buytenhek 479794d15b2SStanislav Samsonov static int __init is_l2_writethrough(void) 480794d15b2SStanislav Samsonov { 481794d15b2SStanislav Samsonov return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); 482794d15b2SStanislav Samsonov } 483794d15b2SStanislav Samsonov 484794d15b2SStanislav Samsonov void __init mv78xx0_init(void) 485794d15b2SStanislav Samsonov { 486794d15b2SStanislav Samsonov int core_index; 487794d15b2SStanislav Samsonov int hclk; 488794d15b2SStanislav Samsonov int pclk; 489794d15b2SStanislav Samsonov int l2clk; 490794d15b2SStanislav Samsonov int tclk; 491794d15b2SStanislav Samsonov 492794d15b2SStanislav Samsonov core_index = mv78xx0_core_index(); 493794d15b2SStanislav Samsonov hclk = get_hclk(); 494794d15b2SStanislav Samsonov get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); 495794d15b2SStanislav Samsonov tclk = get_tclk(); 496794d15b2SStanislav Samsonov 497cfdeb637SLennert Buytenhek printk(KERN_INFO "%s ", mv78xx0_id()); 498cfdeb637SLennert Buytenhek printk("core #%d, ", core_index); 499794d15b2SStanislav Samsonov printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); 500794d15b2SStanislav Samsonov printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); 501794d15b2SStanislav Samsonov printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 502794d15b2SStanislav Samsonov printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); 503794d15b2SStanislav Samsonov 504794d15b2SStanislav Samsonov mv78xx0_setup_cpu_mbus(); 505794d15b2SStanislav Samsonov 506794d15b2SStanislav Samsonov #ifdef CONFIG_CACHE_FEROCEON_L2 507794d15b2SStanislav Samsonov feroceon_l2_init(is_l2_writethrough()); 508794d15b2SStanislav Samsonov #endif 509794d15b2SStanislav Samsonov } 510