1 /* 2 * linux/arch/arm/mach-mmp/time.c 3 * 4 * Support for clocksource and clockevents 5 * 6 * Copyright (C) 2008 Marvell International Ltd. 7 * All rights reserved. 8 * 9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> 10 * 2008-10-08: Bin Yang <bin.yang@marvell.com> 11 * 12 * The timers module actually includes three timers, each timer with up to 13 * three match comparators. Timer #0 is used here in free-running mode as 14 * the clock source, and match comparator #1 used as clock event device. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/interrupt.h> 24 #include <linux/clockchips.h> 25 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/sched.h> 29 30 #include <asm/sched_clock.h> 31 #include <mach/addr-map.h> 32 #include <mach/regs-timers.h> 33 #include <mach/regs-apbc.h> 34 #include <mach/irqs.h> 35 #include <mach/cputype.h> 36 #include <asm/mach/time.h> 37 38 #include "clock.h" 39 40 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE 41 42 #define MAX_DELTA (0xfffffffe) 43 #define MIN_DELTA (16) 44 45 static DEFINE_CLOCK_DATA(cd); 46 47 /* 48 * FIXME: the timer needs some delay to stablize the counter capture 49 */ 50 static inline uint32_t timer_read(void) 51 { 52 int delay = 100; 53 54 __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0)); 55 56 while (delay--) 57 cpu_relax(); 58 59 return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0)); 60 } 61 62 unsigned long long notrace sched_clock(void) 63 { 64 u32 cyc = timer_read(); 65 return cyc_to_sched_clock(&cd, cyc, (u32)~0); 66 } 67 68 static void notrace mmp_update_sched_clock(void) 69 { 70 u32 cyc = timer_read(); 71 update_sched_clock(&cd, cyc, (u32)~0); 72 } 73 74 static irqreturn_t timer_interrupt(int irq, void *dev_id) 75 { 76 struct clock_event_device *c = dev_id; 77 78 /* disable and clear pending interrupt status */ 79 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); 80 __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0)); 81 c->event_handler(c); 82 return IRQ_HANDLED; 83 } 84 85 static int timer_set_next_event(unsigned long delta, 86 struct clock_event_device *dev) 87 { 88 unsigned long flags, next; 89 90 local_irq_save(flags); 91 92 /* clear pending interrupt status and enable */ 93 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); 94 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0)); 95 96 next = timer_read() + delta; 97 __raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0)); 98 99 local_irq_restore(flags); 100 return 0; 101 } 102 103 static void timer_set_mode(enum clock_event_mode mode, 104 struct clock_event_device *dev) 105 { 106 unsigned long flags; 107 108 local_irq_save(flags); 109 switch (mode) { 110 case CLOCK_EVT_MODE_ONESHOT: 111 case CLOCK_EVT_MODE_UNUSED: 112 case CLOCK_EVT_MODE_SHUTDOWN: 113 /* disable the matching interrupt */ 114 __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0)); 115 break; 116 case CLOCK_EVT_MODE_RESUME: 117 case CLOCK_EVT_MODE_PERIODIC: 118 break; 119 } 120 local_irq_restore(flags); 121 } 122 123 static struct clock_event_device ckevt = { 124 .name = "clockevent", 125 .features = CLOCK_EVT_FEAT_ONESHOT, 126 .shift = 32, 127 .rating = 200, 128 .set_next_event = timer_set_next_event, 129 .set_mode = timer_set_mode, 130 }; 131 132 static cycle_t clksrc_read(struct clocksource *cs) 133 { 134 return timer_read(); 135 } 136 137 static struct clocksource cksrc = { 138 .name = "clocksource", 139 .rating = 200, 140 .read = clksrc_read, 141 .mask = CLOCKSOURCE_MASK(32), 142 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 143 }; 144 145 static void __init timer_config(void) 146 { 147 uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR); 148 uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER); 149 uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR); 150 151 __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ 152 153 ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3); 154 __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); 155 156 /* free-running mode */ 157 __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR); 158 159 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */ 160 __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */ 161 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); 162 163 /* enable timer counter */ 164 __raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER); 165 } 166 167 static struct irqaction timer_irq = { 168 .name = "timer", 169 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 170 .handler = timer_interrupt, 171 .dev_id = &ckevt, 172 }; 173 174 void __init timer_init(int irq) 175 { 176 timer_config(); 177 178 init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE); 179 180 ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); 181 ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); 182 ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); 183 ckevt.cpumask = cpumask_of(0); 184 185 setup_irq(irq, &timer_irq); 186 187 clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); 188 clockevents_register_device(&ckevt); 189 } 190