1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-mmp/time.c 4 * 5 * Support for clocksource and clockevents 6 * 7 * Copyright (C) 2008 Marvell International Ltd. 8 * All rights reserved. 9 * 10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> 11 * 2008-10-08: Bin Yang <bin.yang@marvell.com> 12 * 13 * The timers module actually includes three timers, each timer with up to 14 * three match comparators. Timer #0 is used here in free-running mode as 15 * the clock source, and match comparator #1 used as clock event device. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/interrupt.h> 21 #include <linux/clockchips.h> 22 #include <linux/clk.h> 23 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/sched_clock.h> 30 #include <asm/mach/time.h> 31 32 #include "addr-map.h" 33 #include "regs-timers.h" 34 #include "regs-apbc.h" 35 #include "irqs.h" 36 #include <linux/soc/mmp/cputype.h> 37 38 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE 39 40 #define MAX_DELTA (0xfffffffe) 41 #define MIN_DELTA (16) 42 43 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; 44 45 /* 46 * Read the timer through the CVWR register. Delay is required after requesting 47 * a read. The CR register cannot be directly read due to metastability issues 48 * documented in the PXA168 software manual. 49 */ 50 static inline uint32_t timer_read(void) 51 { 52 uint32_t val; 53 int delay = 3; 54 55 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); 56 57 while (delay--) 58 val = __raw_readl(mmp_timer_base + TMR_CVWR(1)); 59 60 return val; 61 } 62 63 static u64 notrace mmp_read_sched_clock(void) 64 { 65 return timer_read(); 66 } 67 68 static irqreturn_t timer_interrupt(int irq, void *dev_id) 69 { 70 struct clock_event_device *c = dev_id; 71 72 /* 73 * Clear pending interrupt status. 74 */ 75 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); 76 77 /* 78 * Disable timer 0. 79 */ 80 __raw_writel(0x02, mmp_timer_base + TMR_CER); 81 82 c->event_handler(c); 83 84 return IRQ_HANDLED; 85 } 86 87 static int timer_set_next_event(unsigned long delta, 88 struct clock_event_device *dev) 89 { 90 unsigned long flags; 91 92 local_irq_save(flags); 93 94 /* 95 * Disable timer 0. 96 */ 97 __raw_writel(0x02, mmp_timer_base + TMR_CER); 98 99 /* 100 * Clear and enable timer match 0 interrupt. 101 */ 102 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); 103 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); 104 105 /* 106 * Setup new clockevent timer value. 107 */ 108 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); 109 110 /* 111 * Enable timer 0. 112 */ 113 __raw_writel(0x03, mmp_timer_base + TMR_CER); 114 115 local_irq_restore(flags); 116 117 return 0; 118 } 119 120 static int timer_set_shutdown(struct clock_event_device *evt) 121 { 122 unsigned long flags; 123 124 local_irq_save(flags); 125 /* disable the matching interrupt */ 126 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); 127 local_irq_restore(flags); 128 129 return 0; 130 } 131 132 static struct clock_event_device ckevt = { 133 .name = "clockevent", 134 .features = CLOCK_EVT_FEAT_ONESHOT, 135 .rating = 200, 136 .set_next_event = timer_set_next_event, 137 .set_state_shutdown = timer_set_shutdown, 138 .set_state_oneshot = timer_set_shutdown, 139 }; 140 141 static u64 clksrc_read(struct clocksource *cs) 142 { 143 return timer_read(); 144 } 145 146 static struct clocksource cksrc = { 147 .name = "clocksource", 148 .rating = 200, 149 .read = clksrc_read, 150 .mask = CLOCKSOURCE_MASK(32), 151 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 152 }; 153 154 static void __init timer_config(void) 155 { 156 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); 157 158 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ 159 160 ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ? 161 (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : 162 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); 163 __raw_writel(ccr, mmp_timer_base + TMR_CCR); 164 165 /* set timer 0 to periodic mode, and timer 1 to free-running mode */ 166 __raw_writel(0x2, mmp_timer_base + TMR_CMR); 167 168 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */ 169 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */ 170 __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); 171 172 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */ 173 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */ 174 __raw_writel(0x0, mmp_timer_base + TMR_IER(1)); 175 176 /* enable timer 1 counter */ 177 __raw_writel(0x2, mmp_timer_base + TMR_CER); 178 } 179 180 void __init mmp_timer_init(int irq, unsigned long rate) 181 { 182 timer_config(); 183 184 sched_clock_register(mmp_read_sched_clock, 32, rate); 185 186 ckevt.cpumask = cpumask_of(0); 187 188 if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, 189 "timer", &ckevt)) 190 pr_err("Failed to request irq %d (timer)\n", irq); 191 192 clocksource_register_hz(&cksrc, rate); 193 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA); 194 } 195 196 static int __init mmp_dt_init_timer(struct device_node *np) 197 { 198 struct clk *clk; 199 int irq, ret; 200 unsigned long rate; 201 202 clk = of_clk_get(np, 0); 203 if (!IS_ERR(clk)) { 204 ret = clk_prepare_enable(clk); 205 if (ret) 206 return ret; 207 rate = clk_get_rate(clk); 208 } else if (cpu_is_pj4()) { 209 rate = 6500000; 210 } else { 211 rate = 3250000; 212 } 213 214 irq = irq_of_parse_and_map(np, 0); 215 if (!irq) 216 return -EINVAL; 217 218 mmp_timer_base = of_iomap(np, 0); 219 if (!mmp_timer_base) 220 return -ENOMEM; 221 222 mmp_timer_init(irq, rate); 223 return 0; 224 } 225 226 TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer); 227