1if ARCH_IXP4XX 2 3config ARCH_SUPPORTS_BIG_ENDIAN 4 bool 5 default y 6 7menu "Intel IXP4xx Implementation Options" 8 9comment "IXP4xx Platforms" 10 11config MACH_NSLU2 12 bool 13 prompt "Linksys NSLU2" 14 select PCI 15 help 16 Say 'Y' here if you want your kernel to support Linksys's 17 NSLU2 NAS device. For more information on this platform, 18 see http://www.nslu2-linux.org 19 20config ARCH_AVILA 21 bool "Avila" 22 select PCI 23 help 24 Say 'Y' here if you want your kernel to support the Gateworks 25 Avila Network Platform. For more information on this platform, 26 see <file:Documentation/arm/IXP4xx>. 27 28config ARCH_ADI_COYOTE 29 bool "Coyote" 30 select PCI 31 help 32 Say 'Y' here if you want your kernel to support the ADI 33 Engineering Coyote Gateway Reference Platform. For more 34 information on this platform, see <file:Documentation/arm/IXP4xx>. 35 36config ARCH_IXDP425 37 bool "IXDP425" 38 select PCI 39 help 40 Say 'Y' here if you want your kernel to support Intel's 41 IXDP425 Development Platform (Also known as Richfield). 42 For more information on this platform, see <file:Documentation/arm/IXP4xx>. 43 44config MACH_IXDPG425 45 bool "IXDPG425" 46 select PCI 47 help 48 Say 'Y' here if you want your kernel to support Intel's 49 IXDPG425 Development Platform (Also known as Montajade). 50 For more information on this platform, see <file:Documentation/arm/IXP4xx>. 51 52config MACH_IXDP465 53 bool "IXDP465" 54 select PCI 55 help 56 Say 'Y' here if you want your kernel to support Intel's 57 IXDP465 Development Platform (Also known as BMP). 58 For more information on this platform, see <file:Documentation/arm/IXP4xx>. 59 60 61# 62# IXCDP1100 is the exact same HW as IXDP425, but with a different machine 63# number from the bootloader due to marketing monkeys, so we just enable it 64# by default if IXDP425 is enabled. 65# 66config ARCH_IXCDP1100 67 bool 68 depends on ARCH_IXDP425 69 default y 70 71config ARCH_PRPMC1100 72 bool "PrPMC1100" 73 help 74 Say 'Y' here if you want your kernel to support the Motorola 75 PrPCM1100 Processor Mezanine Module. For more information on 76 this platform, see <file:Documentation/arm/IXP4xx>. 77 78config MACH_NAS100D 79 bool 80 prompt "NAS100D" 81 select PCI 82 help 83 Say 'Y' here if you want your kernel to support Iomega's 84 NAS 100d device. For more information on this platform, 85 see http://www.nslu2-linux.org/wiki/NAS100d/HomePage 86 87# 88# Avila and IXDP share the same source for now. Will change in future 89# 90config ARCH_IXDP4XX 91 bool 92 depends on ARCH_IXDP425 || ARCH_AVILA || MACH_IXDP465 93 default y 94 95# 96# Certain registers and IRQs are only enabled if supporting IXP465 CPUs 97# 98config CPU_IXP46X 99 bool 100 depends on MACH_IXDP465 101 default y 102 103config MACH_GTWX5715 104 bool "Gemtek WX5715 (Linksys WRV54G)" 105 depends on ARCH_IXP4XX 106 select PCI 107 help 108 This board is currently inside the Linksys WRV54G Gateways. 109 110 IXP425 - 266mhz 111 32mb SDRAM 112 8mb Flash 113 miniPCI slot 0 does not have a card connector soldered to the board 114 miniPCI slot 1 has an ISL3880 802.11g card (Prism54) 115 npe0 is connected to a Kendin KS8995M Switch (4 ports) 116 npe1 is the "wan" port 117 "Console" UART is available on J11 as console 118 "High Speed" UART is n/c (as far as I can tell) 119 20 Pin ARM/Xscale JTAG interface on J2 120 121comment "IXP4xx Options" 122 123config DMABOUNCE 124 bool 125 default y 126 depends on PCI 127 128config IXP4XX_INDIRECT_PCI 129 bool "Use indirect PCI memory access" 130 depends on PCI 131 help 132 IXP4xx provides two methods of accessing PCI memory space: 133 134 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). 135 To access PCI via this space, we simply ioremap() the BAR 136 into the kernel and we can use the standard read[bwl]/write[bwl] 137 macros. This is the preferred method due to speed but it 138 limits the system to just 64MB of PCI memory. This can be 139 problamatic if using video cards and other memory-heavy devices. 140 141 2) If > 64MB of memory space is required, the IXP4xx can be 142 configured to use indirect registers to access PCI This allows 143 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 144 The disadvantage of this is that every PCI access requires 145 three local register accesses plus a spinlock, but in some 146 cases the performance hit is acceptable. In addition, you cannot 147 mmap() PCI devices in this case due to the indirect nature 148 of the PCI window. 149 150 By default, the direct method is used. Choose this option if you 151 need to use the indirect method instead. If you don't know 152 what you need, leave this option unselected. 153 154endmenu 155 156endif 157