1if ARCH_IXP4XX 2 3config ARCH_SUPPORTS_BIG_ENDIAN 4 bool 5 default y 6 7menu "Intel IXP4xx Implementation Options" 8 9comment "IXP4xx Platforms" 10 11# This entry is placed on top because otherwise it would have 12# been shown as a submenu. 13config MACH_NSLU2 14 bool 15 prompt "NSLU2" if !(MACH_IXDP465 || MACH_IXDPG425 || ARCH_IXDP425 || ARCH_ADI_COYOTE || ARCH_AVILA || ARCH_IXCDP1100 || ARCH_PRPMC1100 || MACH_GTWX5715) 16 help 17 Say 'Y' here if you want your kernel to support Linksys's 18 NSLU2 NAS device. For more information on this platform, 19 see http://www.nslu2-linux.org 20 21config ARCH_AVILA 22 bool "Avila" 23 help 24 Say 'Y' here if you want your kernel to support the Gateworks 25 Avila Network Platform. For more information on this platform, 26 see <file:Documentation/arm/IXP4xx>. 27 28config ARCH_ADI_COYOTE 29 bool "Coyote" 30 help 31 Say 'Y' here if you want your kernel to support the ADI 32 Engineering Coyote Gateway Reference Platform. For more 33 information on this platform, see <file:Documentation/arm/IXP4xx>. 34 35config ARCH_IXDP425 36 bool "IXDP425" 37 help 38 Say 'Y' here if you want your kernel to support Intel's 39 IXDP425 Development Platform (Also known as Richfield). 40 For more information on this platform, see <file:Documentation/arm/IXP4xx>. 41 42config MACH_IXDPG425 43 bool "IXDPG425" 44 help 45 Say 'Y' here if you want your kernel to support Intel's 46 IXDPG425 Development Platform (Also known as Montajade). 47 For more information on this platform, see <file:Documentation/arm/IXP4xx>. 48 49config MACH_IXDP465 50 bool "IXDP465" 51 help 52 Say 'Y' here if you want your kernel to support Intel's 53 IXDP465 Development Platform (Also known as BMP). 54 For more information on this platform, see <file:Documentation/arm/IXP4xx>. 55 56 57# 58# IXCDP1100 is the exact same HW as IXDP425, but with a different machine 59# number from the bootloader due to marketing monkeys, so we just enable it 60# by default if IXDP425 is enabled. 61# 62config ARCH_IXCDP1100 63 bool 64 depends on ARCH_IXDP425 65 default y 66 67config ARCH_PRPMC1100 68 bool "PrPMC1100" 69 help 70 Say 'Y' here if you want your kernel to support the Motorola 71 PrPCM1100 Processor Mezanine Module. For more information on 72 this platform, see <file:Documentation/arm/IXP4xx>. 73 74config MACH_NAS100D 75 bool 76 prompt "NAS100D" 77 help 78 Say 'Y' here if you want your kernel to support Iomega's 79 NAS 100d device. For more information on this platform, 80 see http://www.nslu2-linux.org/wiki/NAS100d/HomePage 81 82# 83# Avila and IXDP share the same source for now. Will change in future 84# 85config ARCH_IXDP4XX 86 bool 87 depends on ARCH_IXDP425 || ARCH_AVILA || MACH_IXDP465 88 default y 89 90# 91# Certain registers and IRQs are only enabled if supporting IXP465 CPUs 92# 93config CPU_IXP46X 94 bool 95 depends on MACH_IXDP465 96 default y 97 98config MACH_GTWX5715 99 bool "Gemtek WX5715 (Linksys WRV54G)" 100 depends on ARCH_IXP4XX 101 help 102 This board is currently inside the Linksys WRV54G Gateways. 103 104 IXP425 - 266mhz 105 32mb SDRAM 106 8mb Flash 107 miniPCI slot 0 does not have a card connector soldered to the board 108 miniPCI slot 1 has an ISL3880 802.11g card (Prism54) 109 npe0 is connected to a Kendin KS8995M Switch (4 ports) 110 npe1 is the "wan" port 111 "Console" UART is available on J11 as console 112 "High Speed" UART is n/c (as far as I can tell) 113 20 Pin ARM/Xscale JTAG interface on J2 114 115 116comment "IXP4xx Options" 117 118config IXP4XX_INDIRECT_PCI 119 bool "Use indirect PCI memory access" 120 help 121 IXP4xx provides two methods of accessing PCI memory space: 122 123 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). 124 To access PCI via this space, we simply ioremap() the BAR 125 into the kernel and we can use the standard read[bwl]/write[bwl] 126 macros. This is the preferred method due to speed but it 127 limits the system to just 64MB of PCI memory. This can be 128 problamatic if using video cards and other memory-heavy devices. 129 130 2) If > 64MB of memory space is required, the IXP4xx can be 131 configured to use indirect registers to access PCI This allows 132 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 133 The disadvantadge of this is that every PCI access requires 134 three local register accesses plus a spinlock, but in some 135 cases the performance hit is acceptable. In addition, you cannot 136 mmap() PCI devices in this case due to the indirect nature 137 of the PCI window. 138 139 By default, the direct method is used. Choose this option if you 140 need to use the indirect method instead. If you don't know 141 what you need, leave this option unselected. 142 143endmenu 144 145endif 146