1 /* 2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/device.h> 16 #include <linux/errno.h> 17 #include <linux/io.h> 18 #include <linux/irqdomain.h> 19 #include <linux/of.h> 20 21 #include <asm/mach/irq.h> 22 #include <asm/exception.h> 23 24 #include "common.h" 25 #include "hardware.h" 26 #include "irq-common.h" 27 28 /* 29 ***************************************** 30 * TZIC Registers * 31 ***************************************** 32 */ 33 34 #define TZIC_INTCNTL 0x0000 /* Control register */ 35 #define TZIC_INTTYPE 0x0004 /* Controller Type register */ 36 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ 37 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ 38 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ 39 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ 40 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ 41 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ 42 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ 43 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ 44 #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ 45 #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ 46 #define TZIC_PND0 0x0D00 /* Pending Register 0 */ 47 #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */ 48 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ 49 #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ 50 #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ 51 52 static void __iomem *tzic_base; 53 static struct irq_domain *domain; 54 55 #define TZIC_NUM_IRQS 128 56 57 #ifdef CONFIG_FIQ 58 static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) 59 { 60 unsigned int index, mask, value; 61 62 index = irq >> 5; 63 if (unlikely(index >= 4)) 64 return -EINVAL; 65 mask = 1U << (irq & 0x1F); 66 67 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; 68 if (type) 69 value &= ~mask; 70 __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); 71 72 return 0; 73 } 74 #else 75 #define tzic_set_irq_fiq NULL 76 #endif 77 78 #ifdef CONFIG_PM 79 static void tzic_irq_suspend(struct irq_data *d) 80 { 81 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 82 int idx = d->hwirq >> 5; 83 84 __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); 85 } 86 87 static void tzic_irq_resume(struct irq_data *d) 88 { 89 int idx = d->hwirq >> 5; 90 91 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), 92 tzic_base + TZIC_WAKEUP0(idx)); 93 } 94 95 #else 96 #define tzic_irq_suspend NULL 97 #define tzic_irq_resume NULL 98 #endif 99 100 static struct mxc_extra_irq tzic_extra_irq = { 101 #ifdef CONFIG_FIQ 102 .set_irq_fiq = tzic_set_irq_fiq, 103 #endif 104 }; 105 106 static __init void tzic_init_gc(int idx, unsigned int irq_start) 107 { 108 struct irq_chip_generic *gc; 109 struct irq_chip_type *ct; 110 111 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, 112 handle_level_irq); 113 gc->private = &tzic_extra_irq; 114 gc->wake_enabled = IRQ_MSK(32); 115 116 ct = gc->chip_types; 117 ct->chip.irq_mask = irq_gc_mask_disable_reg; 118 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 119 ct->chip.irq_set_wake = irq_gc_set_wake; 120 ct->chip.irq_suspend = tzic_irq_suspend; 121 ct->chip.irq_resume = tzic_irq_resume; 122 ct->regs.disable = TZIC_ENCLEAR0(idx); 123 ct->regs.enable = TZIC_ENSET0(idx); 124 125 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 126 } 127 128 static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) 129 { 130 u32 stat; 131 int i, irqofs, handled; 132 133 do { 134 handled = 0; 135 136 for (i = 0; i < 4; i++) { 137 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & 138 __raw_readl(tzic_base + TZIC_INTSEC0(i)); 139 140 while (stat) { 141 handled = 1; 142 irqofs = fls(stat) - 1; 143 handle_IRQ(irq_find_mapping(domain, 144 irqofs + i * 32), regs); 145 stat &= ~(1 << irqofs); 146 } 147 } 148 } while (handled); 149 } 150 151 /* 152 * This function initializes the TZIC hardware and disables all the 153 * interrupts. It registers the interrupt enable and disable functions 154 * to the kernel for each interrupt source. 155 */ 156 void __init tzic_init_irq(void __iomem *irqbase) 157 { 158 struct device_node *np; 159 int irq_base; 160 int i; 161 162 tzic_base = irqbase; 163 /* put the TZIC into the reset value with 164 * all interrupts disabled 165 */ 166 i = __raw_readl(tzic_base + TZIC_INTCNTL); 167 168 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); 169 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); 170 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); 171 172 for (i = 0; i < 4; i++) 173 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); 174 175 /* disable all interrupts */ 176 for (i = 0; i < 4; i++) 177 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); 178 179 /* all IRQ no FIQ Warning :: No selection */ 180 181 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); 182 WARN_ON(irq_base < 0); 183 184 np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); 185 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, 186 &irq_domain_simple_ops, NULL); 187 WARN_ON(!domain); 188 189 for (i = 0; i < 4; i++, irq_base += 32) 190 tzic_init_gc(i, irq_base); 191 192 set_handle_irq(tzic_handle_irq); 193 194 #ifdef CONFIG_FIQ 195 /* Initialize FIQ */ 196 init_FIQ(FIQ_START); 197 #endif 198 199 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 200 } 201 202 /** 203 * tzic_enable_wake() - enable wakeup interrupt 204 * 205 * @return 0 if successful; non-zero otherwise 206 * 207 * This function provides an interrupt synchronization point that is required 208 * by tzic enabled platforms before entering imx specific low power modes (ie, 209 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode). 210 */ 211 int tzic_enable_wake(void) 212 { 213 unsigned int i; 214 215 __raw_writel(1, tzic_base + TZIC_DSMINT); 216 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) 217 return -EAGAIN; 218 219 for (i = 0; i < 4; i++) 220 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), 221 tzic_base + TZIC_WAKEUP0(i)); 222 223 return 0; 224 } 225